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2018-07-19ec/lenovo/h8/acpi: Apply state on wakePatrick Rudolph
Implement ACPI S3 resume control to restore the state before entering sleep. * Store the requested state wake state for bluetooth and WWAN. * Add new methods to init the state and apply the requested state on wake. * Call the new method on all devices. Change-Id: I13c08b8c6b1bf0f3deb25a464b26880d8469c005 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19ec/lenovo/h8/ssdt: Add UWB ACPI interfacePatrick Rudolph
Add ACPI methods GUWB and SUWB for thinkpad_acpi. Required for power control of the UWB module. Change-Id: I8f9a56e45c0d765b0e06b8d3600bd3575dd09491 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19ec/lenovo/h8/ssdt: Add keyboard backlight interfacePatrick Rudolph
Add methods MLCG and MLCS for thinkpad_acpi kernel module. Required for backlight or thinklight control from userspace. Change-Id: Ia65e770e772936c9c32be33c30839a2dee2a107c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19ec/lenovo/h8/acpi: Add WWAN ACPI methodsPatrick Rudolph
Implement GWAN and SWAN for thinkpad_acpi kernel module. Both methods allow power control of the WWAN module. Change-Id: I5550c78e0d36884eca7a8d8ece19b64aaee44045 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-09src/{ec,include,lib}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I447aaa1850b7e8b514a8c4c04bf5b426d3d1cd0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09ec/lenovo/h8/acpi: Add BDC interfacePatrick Rudolph
* Add SSDT generator to add dynamic ACPI code. * Implement GBDC and SBDC for thinkpad_acpi kernel module. Required for BDC power control from userspace. Tested on Lenovo T430: The bluetooth module is detected and can be powercycled using network manager. Change-Id: Ida825196650966194a883945896a038b0790fe45 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-06ec/lenovo/h8/acpi: Move ACPI HKEY device to new filePatrick Rudolph
Move the APCI HKEY device to a new file and include it. The follow-up commits will extend it and this way it remains readable. Change-Id: Ie59b59e5a4148807125c71a362161026f685a97e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2018-07-03ec/google/chromeec: Remove keyboard initializationFurquan Shaikh
Since none of the boards using chromeec select DRIVERS_PS2_KEYBOARD now, there is no need to call pc_keyboard_init anymore. This change gets rid of the call and adds an error message in case any mainboard using chromeec tries to select this config. BUG=b:110024487 Change-Id: Ia0b56abe0a5990e527277eaf3397e00dccda3e50 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-02ec/google/chromeec: Remove notify for power buttonFurquan Shaikh
None of the mainboards using Chrome EC set SCI mask for power button. Thus, the EC will never generate SCI for power button events. This change removes the Notify call for power button as part of clean up for getting rid of the power button device in coreboot. BUG=b:110913245 Change-Id: I86c72fd82f1a0e6d5693ebbcd58e2aea808f8817 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-07google/chromeec: Set proper dev opsNaresh G Solanki
For enable_resource & set_resource, use default DEVICE_NOOP so that they are not reported as missing during enumeration. BUG=None BRANCH=None TEST= Build & boot soraka. Change-Id: I0fcfb8df39c6313c8a5bab5b780a8ffa7531d210 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26869 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04src/ec: Remove whitespace before tabElyes HAOUAS
Change-Id: Ib47cc1ee617aae74a8cfbcb25c1d0c083196f417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-01ec/google/chromeec: Initialize SMI mask in google_chromeec_events_initFurquan Shaikh
This change adds smi_events to google_chromeec_event_info and allows mainboards to set SMI mask if current boot type is not S3 wakeup. Change-Id: I899a6af6e57d295b4eac2039c8245ebcc73a42bb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-29chromeec platforms: Update ACPI throttle handler callMartin Roth
Currently the throttle event handler method THRT is defined as an extern, then defined again in the platform with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I6337c52edaf9350843848b31c5d87bbfca403930 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-24src: Remove space after `defined`Elyes HAOUAS
Change-Id: If450a68e98261ffba4afadbce47c156c7e89e7e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26460 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24chromeec: Add support for controlling USB port powerEmil Lundmark
This maps a bit field to the EC (EC_ACPI_MEM_USB_PORT_POWER) that can be used to control the power state of up to 8 individual USB ports. Some Chromeboxes have their GPIO pins for controlling USB port power wired to the EC, so they cannot be accessed directly by coreboot. Change-Id: I6a362c2b868b296031a4170c15e7c0dedbb870b8 Signed-off-by: Emil Lundmark <lndmrk@chromium.org> Reviewed-on: https://review.coreboot.org/26471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-08ec/google/chromeec: add config for wake event typesPatrick Georgi
Avoids array overflow Change-Id: Ia49a782ba6729c740e3b91c500120132983f6b3c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/25992 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08ec/lenovo/h8: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I3db9487c46b29510e59ec5c019d022f5cbaff354 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-03ec/google/chromeec: Update Tablet event callMartin Roth
The tablet event handler method TPET is defined as an extern, then defined again in skylake, the only platform that supports it. In newer versions of IASL, this generates an error, as the method is defined in two places. Remove the extern and the CondRefOf check. That's not needed if we only set the EC_ENABLE_TABLET_EVENT define on platforms that have a TPET handler. Change-Id: I8bee069fc95637446593dfaaae1254e931421517 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-05-01chromeec platforms: Update ACPI thermal event handler callMartin Roth
Currently the thermal event handler method TEVT is defined as an extern, then defined again in platforms with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30cros-ec: Avoid infinitely looping in google_chromeec_pd_get_amodeDaisuke Nojiri
Currently, google_chromeec_pd_get_amode infinitely loops if a TCPC port is connected to a device with alternate mode(s) and the call is made for the mode with the index higher than 0 (e.g. Zinger). Cros EC manages alternative modes entered in an array (amode[]). The command is designed to accept a query for an particular index and a particular SVID. Zinger has a 'Google' mode. It's stored in amode[0]. When AP queries first time for DisplayPort with index=0, EC says 'no' as expected. AP sends the next query with index=1 but EC_CMD_PROTO_VERSION (0x00) is sent instead because cmd_code is cleared by google_chromeec_command. res.svid is supposed to be 0 when EC hits the last index + 1 but res.svid is set to 2 by the EC_CMD_PROTO_VERSION handler because EC_PROTO_VERSION is currently 2. So, the call succeeds and AP goes to the next index and this repeats forever. Any USB-C device with non-DisplayPort alternate mode can cause this hang unless HDMI port is used. This patch resets all the fields of chromeec_command in each iteration in case google_chromeec_command changes them. BUG=b:78630899 BRANCH=none TEST=Verify Fizz boots without monitors on Zinger. Verify the svid enumeration happens as expected. Change-Id: I388ed4bdfac9176d8e690c429e99674ed267004f Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/25878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-01chromeec: fix an uninitialized local variableZhuohao Lee
google_chromeec_command() may only write the 1 or 2 bytes to variable r (4 bytes). However, this api returns 4 bytes data. To avaid returning the incorrect data, we need to initialize the local variable. BUG=b:76442548 BRANCH=none TEST=write 2 bytes data into the flash, then, read by cbi_get_uint32 Change-Id: I3395c97ab6bfd7882d7728310de8a29041190e76 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/25460 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-26ec/purism: Fix CPU Turbo value (PPCM) set by the ECYouness Alaoui
The EC needs to set the PPCM value depending on whether Turbo is enabled or not, and the values differ between Broadwell (0, 1) and Skylake (1, 2) platforms. Change-Id: I662dce54415e685c054ffc00b6afde0f1f7765e2 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-03-09ec/google/chromeec: Add boardid.c to bootblockMartin Roth
Update build so that we can get the board ID in bootblock. BUG=b:74248569 TEST=build and boot grunt with follow-on patch. Bayhub part is disabled. Change-Id: I6353bcb4abcef4e8dc2b625082e33b73525c8525 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-07ec/google/chromeec: Fix typo preventing PD EC firmware inclusionBen Pye
Change-Id: I12ae0d556c43d3d6537cac5d8f640e6a960101ae Signed-off-by: Ben Pye <ben@curlybracket.co.uk> Reviewed-on: https://review.coreboot.org/25017 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06mainboard/google/fizz: Check HDMI HPD and DisplayPort HPDDaisuke Nojiri
Some type-c monitors do not immediately assert HPD. If we continue to boot without HPD asserted, Depthcharge fails to show pictures on a monitor even if HPD is asserted later. Also, if an HDMI monitor is connected, no wait is needed. If only an HDMI monitor is connected, currently the API always loops until the stopwatch expires. This patch will make the AP skip DisplayPort wait loop if it detects an HDMI monitor. And if an HDMI monitor is not detected, the AP will wait for DisplayPort mode (like before) but also its HPD signal. This patch also extends the wait loop time-out to 3 seconds. BUG=b:72387533 BRANCH=none TEST=Verify firmware screen is displayed even when a type-c monitor does not immediately assert HPD. Verify if HDMI monitor is connected, AP does not wait (and firmware screen is displayed on HDMI monitor). Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-05ec/chromeec: Fix check for UHEPI supportMatt DeVillier
Commit 1dfc2c3 [google/chromeec: Enable unified host event programming interface] added support for UHEPI, but google_chromeec_is_uhepi_supported() incorrectly treats negative error return codes from google_chromeec_check_feature() as supported. Fix this check to only treat positive return values as supported, as per the original intent. Test: boot google/lulu, verify cbmem console reports UHEPI not supported even if feature check returns error code, verify lid/kb wake events correctly wakes the device from S3/sleep. Change-Id: I7846efb340bc1546b074e8502daf906c444bd146 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24982 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02ec/google/chromeec: Add note before error messageMartin Roth
When clearing events from the EC, an error is returned when we try to clear an event that doesn't exist. This is normal, but can be distracting when trying to track down an error, so add a message saying that the error is expected. BUG=None Test=Build Grunt with SMM debug enabled. See message before "EC returned error result code 1". Change-Id: Ib2e684e357e821c795de4b59658432c91a8d63fc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/24914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-26ec/google/chromeec: Remove extra newline characters from printkFurquan Shaikh
This change removes extra newline characters from print statements for wake masks. Change-Id: I13cde76bfb0f10b1dda8117c27f2891e909f9669 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-17chromeec: Sync ec_commands.h for CBI tagsDaisuke Nojiri
This patch syncs ec_commands.h with the one in chromeec. BUG=b:70294260 BRANCH=none TEST=Verify SKU_ID and OEM_ID are correctly recognized on Fizz. Change-Id: I451ec9f6f9d7257915b7d4cb1e5adbee82d107de Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-17chromeec: Add google_chromeec_wait_for_displayDaisuke Nojiri
The google_chromeec_wait_for_display API checks whether a display is ready or not. It waits in a loop until EC says it entered DisplayPort alternative mode or times out in 2 seconds. BUG=b:72387533 BRANCH=none TEST=See 23746 "mb/google/fizz: Wait until display is ready" Change-Id: Ieee5db77bd6e147936ea8fc735dcbeffec98c0f8 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-17chromeec: Add google_chromeec_pd_get_amodeDaisuke Nojiri
The google_chromeec_pd_get_amode API checks whether TCPM is in a specified alternate mode or not. BUG=b:72387533 BRANCH=none TEST=See 23746 "mb/google/fizz: Wait until display is ready" Change-Id: Ib9b4ad06b61326fa167c77758603e038d817f928 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-12ec/chromeec: Fix battery ACPI mutex levelMatt DeVillier
Commit 07fe618 [chromeec: Add support for reading second battery info] added a mutex as part of the ACPI code to determine battery statuses. Windows is extremely picky about ACPI code, and attempting to acquire a level 1 mutex without first having acquired a level 0 mutex causes Windows to hang on boot. Since there's no reason to use a level 1 mutex here, change it to level 0. Test: Boot Windows on device with ChromeEC without hanging Change-Id: Icfb0817cfe0c49eb4527a12b507362939a6d32c6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-09chromeec: Fix ACPI compile warningLijian Zhao
For system without secondary battery, current DSDT will report warning during build time. Add a conditional check to make sure only battery index 0 can return success. TEST=Build pass. Change-Id: Iae12c5d1aa749948ef4025c8b5e60c97e1b747a5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23661 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07chromeec: Add support for reading second battery infoNicolas Boichat
We share the same shared memory fields for both batteries. When the host wants to switch battery to read out, it will: - Set BTID (EC_ACPI_MEM_BATTERY_INDEX) to the required index - Wait for BITX (EC_MEMMAP_BATT_INDEX) to have the required value - Then fetch the data BRANCH=none BUG=b:65697620 TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are present, data is valid. Change-Id: Ib06176e6ab4c45a899259f0917e6292121865ed6 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/23598 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-02-05ec/google: Get OEM ID and SKU ID from ECDaisuke Nojiri
This patch adds EC_CMD_GET_CROS_BOARD_INFO and two APIs to fetch OEM ID and SKU ID from cros EC. CBI abbreviates Cros Board Info. BUG=b:70294260 BRANCH=none TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz. Change-Id: Iff69a2dc0e562d87dd287f79c407f23aeb09fb9e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-02ec/google/chromeec: Remove wake flag from keyboard IRQDuncan Laurie
The keyboard IRQ was changed to ExclusiveAndWake in order to support waking from suspend-to-idle (S0ix) with commit f611fcfacac5be14a51e04ae4d0b1e25cd5439c0 http://review.coreboot.org/11712 However this is triggering a kernel panic on Windows 10 because it apparently does not like legacy device interrupts to to be set as wake capable. This change is no longer necessary because the linux kernel was changed to always treat the keyboard as wake capable: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/input/serio/i8042.c?id=f13b2065de8147a1652b830ea5db961cf80c09df Change-Id: I26e27de68095f8d176108f39312338522d7cfba0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23563 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-30chromeec: Decouple EC tablet event and TBMC deviceFurquan Shaikh
This change decouples EC tablet event and TBMC device by guarding TBMC definition and notification using EC_ENABLE_TBMC_DEVICE. It allows mainboards to use tablet events without having to define a TBMC device. BUG=b:72554519 Change-Id: Ie38b6d68486e8e644dd0d6d406def3ae7fdb5152 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-26ec/google/chromeec: Add _PRW property to CREC deviceFurquan Shaikh
This change adds _PRW property to CREC device that allows Linux kernel to identify CREC as a wakeup source. BUG=b:69118395 TEST=Verified following steps: 1. Under sys devices for CREC: "echo enabled > wakeup" 2. Lid close/Lid open -- Verified that wakeup_count increases 3. Mode change -- Verified that wakeup_count increases Change-Id: Ib0a687e171c7e5c81325b39f47c9a2462553fe3e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-17google/chromeec: Enable unified host event programming interfaceJenny TC
Unified Host Event Programming Interface (UHEPI) enables a unified host command EC_CMD_PROGRAM_HOST_EVENT to set/get/clear different host events. Old host event commands (0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F) is supported for backward compatibility. But newer version of BIOS/OS is expected to use UHEPI command (EC_CMD_PROGRAM_HOST_EVENT) The UHEPI also enables the active and lazy wake masks. Active wake mask is the mask that is programmed in the LPC driver (i.e. the mask that is actively used by LPC driver for waking the host during suspended state). It is same as the current wake mask that is set by the smihandler on host just before entering sleep state S3/S5. On the other hand, lazy wake masks are per-sleep masks (S0ix, S3, S5) so that they can be used by EC to set the active wake mask depending upon the type of sleep that the host has entered. This allows the host BIOS to perform one-time programming of the wake masks for each supported sleep type and then EC can take care of appropriately setting the active mask when host enters a particular sleep state. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0,S3,S5 and S0ix 1). Verified wake masks with ec hostevent command on S0,S3,S5 and S0ix 2). suspend_stress_test with S3 and S0ix 3). Verified "mosys eventlog list" in S3 and s0ix resume to confirm wake sources (Lid, power buttton and Mode change) 4). Verified "mosys eventlog list" in S5 resume to confirm wake sources (Power Button) 5). Verified above scenarios with combination of Old BIOS + New EC and New BIOS + Old EC Change-Id: I4917a222c79b6aaecb71d7704ffde57bf3bc99d9 Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17ec/h8: Store PWRS and notify CPU on AC power plug/unplug eventsArthur Heymans
PWRS is is the power source gnvs. Notifying CPU is needed to change P- and C-states on these events. Change-Id: I0818d10474523fb14f7ba7cfbf61166b89442083 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-12ec/lenovo/h8: Add support for bluetooth on wifiPatrick Rudolph
The EC does enable bluetooth on wifi cards and BDC at the same time. Check the new Kconfig to support bluetooth on wifi in case no BDC is installed and the BDC detection fails. Change-Id: I23f14c937252a296dc543db49ec9e093e7e24604 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-25ec/hp/kbc1126: change the default offset of the blobsIru Cai
Using Kconfig options USE_OPTION_TABLE, BOOTBLOCK_NORMAL makes the bootblock to 4200 bytes, so the offsets of these blobs need to be put at a lower address. Change-Id: I8754e43ff318a03447633f7a9a8326d315328607 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/22978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-19ec/hp/kbc1126/acpi/battery.asl: Make \ISTR serializedIru Cai
This resolves the IASL remark: dsdt.aml 2141: Method (\ISTR, 2, NotSerialized) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) Change-Id: I36e814acc0746cb011b595493d8254f3fb73baf5 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/21668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-08chromeec: Add command to override charger limitDaisuke Nojiri
This patch adds EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, which overrides the max input current and voltage when a barrel jack adapter supplies power. BUG=b:64442692 BRANCH=none TEST=Boot Fizz. Use chgsup console command to verify the max current and voltage are set as expected. Change-Id: I8c6fc54e519ce13e3db82ee2cecaa96c6eb42d8a Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08cr50: Make EC clear AP_OFF before hibnernateDaisuke Nojiri
This patch makes AP send EC_REBOOT_HIBERNATE_CLEAR_AP_OFF, which makes EC clear AP_OFF flag then hibernate. This is needed to make Chromebox boot when cr50 toggles the EC's reset line after TURN_UPDATE_ON command. BUG=b:69721737 BRANCH=none CQ-DEPEND=CL:802632 TEST=Verify Fizz reboot after cr50 update. Change-Id: I5f590286393ac21382cab64afdccae92d3fc14ba Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07boardid: Minor clean up and standardizationJulius Werner
Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-03ec/lenovo/h8/acpi: Fix regression (MS Windows crash on boot)Patrick Rudolph
Fix a regression introduced by #21227 0709dc04 (ec/lenovo/h8/acpi/thermal: Add ACPI fan control). The commit caused Windows to crash as EC reads aren't allowed in the fan device or it's powerresource's methods. Implement the same approach as all other platforms using a GNVS variable named FLVL instead of reading from EC. In addition to EC reads writing to FIELD elements, in another ACPI scope, seems to be broken. Introduce a new method to set the fan disengage mode. Tested on Windows 7 and Lenovo T500. Change-Id: Ia99f8814ac14194578dcd1aa50a63e3f35c042dd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-11-30chromeec: Notify CREC device of wakeup eventsFurquan Shaikh
Whenever there is a new EC event that could be wake-capable, notify CREC device of this using notification value 0x2 i.e. device wake. This allows Linux kernel to track active_count value correctly for CREC device. BUG=b:69118395 BRANCH=None TEST=Verified on Soraka: 1. Put device into suspend 2. Wake up using mode change/lid open 3. Check that the active_count for GOOG0004 has increased (cat wakeup_sources | grep GOOG0004) Change-Id: I723f7f4e4c99e7a5b57c6296da66cf30cd413c27 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22625 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-22chromeec: Change the API for hostevent/wake masks to handle 64-bitFurquan Shaikh
ChromeEC is getting ready to bump up the hostevents and wake masks to 64-bits. The current commands to program hostevents/wake masks will still operate on 32-bits only. A new EC host command will be added to handle 64-bit hostevents/wake masks. In order to prevent individual callers in coreboot from worrying about 32-bit/64-bit, the same API provided by google/chromeec will be updated to accept 64-bit parameters and return 64-bit values. Internally, host command handlers will take care of masking these parameters/return values to appropriate 32-bit/64-bit values. BUG=b:69329196 Change-Id: If59f3f2b1a2aa5ce95883df3e72efc4a32de1190 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 21:37:56 +0000