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2020-09-07ec/system76: Add console supportJeremy Soller
This adds support for line-buffered console output to System76 EC firmware. Once the print command is received, the EC firmware multiplexes the output to any enabled console on the EC. This can be a memory ringbuffer, a parallel port (using the keyboard connector), or i2c (using the battery connector). Once the entire buffer is sent, it sets the command register to 0, indicating completion. For more information, please see: https://github.com/system76/ec/blob/master/doc/debugging.md Tested on system76/lemp9 with CONSOLE_SYSTEM76_EC enabled. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I861bf3e22f40dd6c3ec7ba1d73711b399358e332 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-14ec/google/chromeec: Add helper to request AP resetKarthikeyan Ramasubramanian
Add a helper function to initiate AP reset through Embedded Controller (EC). BUG=b:162290856 TEST=Ensure that the EC resets AP on boards where the command is supported. Change-Id: I01d7dfec72a8a3f6d2c4844bc062672e494860d8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44188 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26ec/lenovo/h8: Align macro values in one columnPaul Menzel
Change-Id: I5691a582d9a195317994413fff4fd3273413b5fe Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth
The Kconfig lint tool checks for cases of the code using BOOL type Kconfig options directly instead of with CONFIG() and will print out warnings about it. It gets confused by these references in comments and strings. To fix it so that it can find the real issues, just update these as we would with real issues. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove whitespace between 'sizeof' and '('Elyes HAOUAS
Change-Id: Iaf22dc1986427e8aa4521b0e9b40fafa5a29dbbd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove unneeded space in license headerElyes HAOUAS
Change-Id: Iac0f0c3d102a9a900ac168f8be907349d9a3dd42 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43565 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26ec/google/chromeec: Fix loop off-by-one error in DPTF _OSCTim Wawrzynczak
The while loop in \_SB.DPTF._OSC accidentally used <= instead of <, so there was an error indexing into IDSP. BUG=b:162043345 TEST=verify disassembled ASL, as well as no BIOS bug mentioned in /var/log/messages Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I08c4152c59cc9eb13386c825aab983681cfa88ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/43827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-26src: Remove unused 'include <cbmem.h>'Elyes HAOUAS
Change-Id: Ib41341b42904dc3050a97b70966dde7e46057d6b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23ec/system76_ec: add support for System76 ECJeremy Soller
This adds ACPI code for System76 EC and converts system76/lemp9 to use EC_SYSTEM76_EC. Tested on system76/lemp9. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I1f693268d94b693b6764e4a3baf4c3180689f3be Reviewed-on: https://review.coreboot.org/c/coreboot/+/43612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Michael Niewöhner
2020-07-22ec/google/chromeec: Fix Coverity Scan error (BAD_SHIFT)Tim Wawrzynczak
A recent Coverity scan found an issue with the way the EC_HOST_EVENT_MASK macro was being used. It was being passed values between 0 and 63, but since it is doing basically (1ULL << (value - 1)), this caused a shift of -1 when `i` is 0 and also doesn't reach the 63rd bit of the mask. This is fixed by incrementing the start and end conditions of the loop by 1, so the event mask ranges from bits 0 to 63, instead of -1 to 62. Found-by: Coverity CID 1430218 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6a7cfa64545f3d313de24407f0a91b48368f2a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-18ec/google/chromeec: Fix oversights in ec_dptf_helpersTim Wawrzynczak
GTSH was 2 instead of 20 (so it's 2 degrees K hysteresis), and TSRD was accidentally defined to take 0 arguments, instead of 1. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I14d28bacf44ac65043060b8579b3fbcec758c56c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-18ec/google/chromeec: Fix \_SB.DPTF._OSCTim Wawrzynczak
The DPTF._OSC method incorrectly assumed that all available UUIDs would be present in the IDSP package, but this is not always the case. Instead of matching an incoming UUID against an index into IDSP, search the IDSP package for the matching UUID. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I718b6abe09152647b14f7c1405b2d0d20035726b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-07ec/google: Add function ec_fill_dptf_helpers()Tim Wawrzynczak
ec_fill_dptf_helpers() is used to generate all of the "helper" methods that DPTF requires. A system with a Chrome EC is typically in charge of fan PWM control as well as battery charging, so if DPTF needs to manipulate those, then it requires Methods provided by the EC. BUG=b:143539650 TEST=compiles Change-Id: Ib30072d1d0748b31bcab240a0fd0e2f12d34aaa4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41894 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05ec/google/chromeec: Drop codec.aslFurquan Shaikh
This change drops codec.asl file from Chrome EC since it is now unused. Change-Id: I6c2f3e53b14aaf76b9c6d038a732e79a4d7bb2f1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43043 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05ec/google/chromeec: Add driver for audio codec deviceFurquan Shaikh
This change adds driver for audio codec device (HID `GOOG0013`) living behind Chrome EC. This driver generates the required ACPI node for the codec device. In a later change, GOOG0013 device will be dropped the .asl file. Change-Id: Ib2759eac60265ef81df70af1d4f1f72bd9d987e8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43041 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05ec/google/chromeec: Move if EC_GOOGLE_CHROMEEC to i2c_tunnel/KconfigFurquan Shaikh
This change moves `if EC_GOOGLE_CHROMEEC` from chromeec/Kconfig to chromeec/i2c_tunnel/Kconfig. This is done to make it clear that the Kconfig file in i2c_tunnel is sourced unconditionally, but the configs in i2c_tunnel/Kconfig are conditionally defined based on the evaluation of if condition. This change addressed the feedback received on https://review.coreboot.org/c/coreboot/+/40515/11/src/ec/google/chromeec/Kconfig#200. Change-Id: I66cd91d6b1813ff6d0fb7be719e2da65ac6ac23b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43040 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04drivers/intel/pmc_mux: Rename con driver to connTim Wawrzynczak
For historical reasons, Windows has issues with certain names being used for files and directories, 'con' or 'CON' being one of them. Therefore, rename the pmc_mux/con driver to pmc_mux/conn in order to work around this issue. TEST=built volteer (only user of this driver as of now) Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia78dc4efe647c96a7169a3b95fc3b8944d052c83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-06-17ec/google/wilco: Suppress UCSI events in S0ixDuncan Laurie
If a UCSI event comes in when the EC is in S0ix mode then the kernel driver attempts a transaction but fails and this can leave the system in an unexpected state where the only wake source is the power button. This change will not notify the UCSI driver if the EC is in S0ix mode and instead keep track of the event and send it on resume. BUG=b:157923800 TEST=tested on drallion system: 1. Put drallion system into suspend 2. Attach power supply 3. Ensure the system can wake with keypress Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I43acb089385d9b41ac955f053e409daad67423f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14ec/google/chromeec: Call \PNOT () on initializing AC power stateFurquan Shaikh
This change calls \PNOT () method when AC power state is initialized to allow platform code to take appropriate action. BUG=b:157752693 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I089e9096f78728ddc5df2d8cb8f22f65b30b02dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/42315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-08ec/google/chromeec: Append connector device to *-switch propertiesTim Wawrzynczak
The orientation, etc. -switch properties are supposed to use the connector device (underneath the MUX device) that belongs to the port number in question. This patch finds the CONx device and uses that to pass to the acpigen API. BUG=b:154620502 TEST=on Volteer, dump SSDT and verify the *-switch properties point to \_SB.PCI0.PNC.MUX.CON0 and CON1 Change-Id: Ie65c2d750f3d9f83285e0e4cc9642110c804bbad Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-06-06ec/google/wilco: Always use current value of battery status bitMathew King
According to the Wilco EC spec the BTSC bit of PWSR is always cleared when PWSR is read so that battery status change events are only triggered one time. Testing of the Wilco EC has verified this behavior. This changes the way in which the battery status change bit is used from checking the bit state against the previous value to always issuing a battery event when the BTSC bit is set. The other bits in PWSR indicate state directly and do not behave like the BTSC bit. BUG=b:157113138 TEST=Deploy on Drallion and verify that battery events are generated BRANCH=drallion, sarien Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8fbf2ee1158ddd790b04a20b1eb27a6cce4f5c81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-02src: Remove redundant includesElyes HAOUAS
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>, <stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes each time when <types.h> is included. Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-02src: Remove unused 'include <bootstate.h>'Elyes HAOUAS
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02src: Remove unused 'include <bootmode.h>'Elyes HAOUAS
Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41670 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28ec/google/chromeec: Switch to use new acpigen_usb moduleTim Wawrzynczak
Implementation of the ACPI objects for the Type-C Connector Class was added in the previous patch. This patch removes the functionality from the ChromeEC's SSDT generator, and uses acpigen_usb instead. TEST=Verified contents of SSDT are the same. Change-Id: Icdbcee1f989ee3146f7495e08fc13f9386791858 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28ec/google/chromeec: Add new *-switch properties to USBC.CONx devicesTim Wawrzynczak
The Linux ChromeOS EC driver now looks for 3 new properties under each USBC.CONx device contained within the ChromeOS EC device. These properties are just a reference to the device that controls the switches for USB 2/3 muxing, SBU lines, and CC lines. It uses the new function, soc_get_pmc_mux_device() to retrieve the device. Change-Id: I03cd83f9b2901b5583053fac8ab6eab64717a07d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40618 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27ec/google/chromeec/acpi/superio: Add PS/2 Mouse ACPI entryRaul E Rangel
The PNP ID Means: PNP0F13 PS/2 Port for PS/2-style Mice BUG=b:145575366 BRANCH=none TEST=Verified mouse was initialized Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2a4f071ad54730ea75f75ebf1633a4a08f7f2dd0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080664 Tested-by: Martin Roth <martinroth@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Commit-Queue: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41639 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTIONKyösti Mälkki
After removal of CAR_MIGRATION there are no more reasons to carry around ENV_STAGE_HAS_BSS_SECTION=n case. Replace 'MAYBE_STATIC_BSS' with 'static' and remove explicit zero-initializers. Change-Id: I14dd9f52da5b06f0116bd97496cf794e5e71bc37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-26ec/lenovo/h8: Config the ec hardware ids for newer thinkpadsDa Lao
Currently coreboot is using the ec hardware id IBM0068 for all thinkpads, but for newer thinkpads the id maybe LEN0068 or LEN0268. On Windows, the Lenovo Vantage app can't get battery details when using IBM0068. This patch config this id by motherboard. The hardware IDs for the following models can be found by searching for disassembled dsdt.asl on vendor BIOS: (But this info is not easy to find online. So I only changed some of the thinkpads.) T420: https://github.com/tluck/Lenovo-T420-Clover/blob/master/EFI/CLOVER/ACPI/1600x900-EDID/DSDT.edid-2e2-hs.dsl LEN0068 T430: https://github.com/ThiagoSchetini/macosx-thinkpad-t430/blob/master/vanilla%20ACPI%20dsl's/DSDT.dsl LEN0068 T520: Confirmed by Patrick Rudolph LEN0068 W520: Confirmed by Patrick Rudolph LEN0068 T530: Confirmed by Prasun Gera LEN0068 W530: https://bugzilla.kernel.org/show_bug.cgi?id=66731 LEN0068 X230/X230T: https://github.com/tuandzung/ThinkPad-X230-macOS-10.12.x/blob/master/DSDT/DSDT.dsl LEN0068 T440p: https://github.com/doudou/t440p/blob/master/acpi/2.30/dsdt.dsl LEN0068 Signed-off-by: Da Lao <dalao@tutanota.com> Change-Id: I797080ec8ba7ce39d47fe587319f8f32d6938875 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-05-21ec/google/chromeec/acpi: Add CROS EC CODEC deviceYu-Hsuan Hsu
This is currently used by trembyle. Add it in a common location so other boards can use it. BUG=b:147200751 BRANCH=none TEST=Able to get ec codec on trembyle Change-Id: Ie21cd813b0e3129f1c61d2de199532b25d3c70fa Signed-off-by: Yu-Hsuan Hsu <yuhsuan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2000271 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> Commit-Queue: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41575 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21ec/google/chromeec/i2c_tunnel: Fix missing constRaul E Rangel
This was missed in the refactor. BUG=b:157140753 TEST=Built trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I150e0b8a806042ef8001805eaefbce71dc1be0e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41574 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13ec/lenovo/h8: Reintroduce h8_mb_init() for specific boardsBill XIE
Mainboard specific dock-init mechanism introduced https://review.coreboot.org/c/coreboot/+/36093 works on most boards, but https://ticket.coreboot.org/issues/256 shows that some boards (e.g. x201 and t410) need communication with h8 EC to enable or disable dock, (in dock_connect() and dock_disconnect() respectively) so they must be done after the h8 EC is brought up, which is not garanteed in the above mainboard specific dock-init mechanism. This time, a hook function h8_mb_init() will be called at the end of h8_enable(). (in place of the ancient h8_mainboard_init_dock() removed in CB:36093) Its default implementation is a weak empty function, but could be overrided with a strong one for boards needing to perform actions which should be done after h8 EC is brought up. This should fix the regression detected in https://ticket.coreboot.org/issues/256 Change-Id: I3674fbfeab2ea2cd2a4453a8e77521157d553388 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-05-11treewide: Convert more license headers to SPDX stylePatrick Georgi
Change-Id: Ia3de79c7d71049da00ed108829eac6cb49ff3ed6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41205 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08{drivers,ec/kontron}: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: Ide6cfd6f79bd54f50d9fde37c55f2b0df702478a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: move copyrights and authors to AUTHORSPatrick Georgi
Also split "this is part of" line from copyright notices. Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-04treewide: Drop ACPI_VIDEO_DEVICE macroAngel Pons
It was always defined to the same value, and only used twice. Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40864 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01ec/google/chromeec: Fix incorrect diag messageVictor Ding
The expected error code observed in clear_pending_events() should be EC_RES_UNAVAILABLE(9), not EC_RES_INVALID_COMMAND(1). BUG=b:153896701 Change-Id: I609490ceef675267760d34b5e9775211da93347c Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40900 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28ec/lenovo/h8: Constify struct device * parameter to h8_has_* functionsFurquan Shaikh
h8_has_bdc() and h8_has_wwan() do not need to modify the device structure. Hence, this change makes the struct device * parameter to these functions as const. This is being done in preparation to make struct device * parameter to fill_ssdt as const. Change-Id: Id3d65d2de7b5161b0e7cff26055c00d5dae967dc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40706 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-25mb/lenovo/{x201,t410}: Move ThinkLight codeStefan Ott
This patch moves the code to control the ThinkLight to the common ACPI folder for h8. This reduces code duplication and allows other ThinkPads to include the same code for ThinkLight support. Change-Id: I57de7516051bdcbb23fc21b4de352f265075893b Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-22ec/google/chromeec: Add driver for i2c_tunnel device under Chrome ECFurquan Shaikh
This change enables support for generating ACPI nodes for I2C tunnel for any GOOG0012 device that is sitting behind the Chrome EC. It accepts a config "remote_bus" which allows mainboard to configure the id of the remote bus that is being tunneled. BUG=b:154290952 BRANCH=None TEST=Verified that SSDT node for I2C tunnel behind Chrome EC is generated correctly. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Icfc0ec3725d7f1d20bcb5cb43a0a23aac72bf4eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/40515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-22ec/google/chromeec: Add .scan_bus() callback for Chrome EC deviceFurquan Shaikh
This change adds scan_static_bus() as .scan_bus() callback for Chrome EC device which allows scanning of devices sitting behind the EC using the topology provided by mainboard's devicetree.cb. BUG=b:154290952 TEST=Verified with follow-up changes that devices behind EC are scanned correctly. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Id3630db56774fba1e3fc53bf349588c4c585773b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40514 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22ec/google/chromeec: Fix acpi_name() for Chrome EC deviceFurquan Shaikh
In ACPI tables, Chrome EC device (CREC - HID GOOG0004) is a child of EC device (EC0 - HID PNP0C09). However, in coreboot device tree, there is no separate chip/device for EC0. Thus, acpi_name() needs to return EC0.CREC as the ACPI name for the Chrome EC device. By returning the ACPI name as EC0.CREC, all devices that live under Chrome EC device can simply call acpi_device_path()/acpi_device_scope() to emit the right path/scope. In the future, if we ever add a special chip driver for handling EC0 (HID PNP0C09), then the ACPI name for Chrome EC can be fixed to return CREC. BUG=b:154290952 TEST=Verified that acpi_device_path()/acpi_device_scope() return the correct name for Chrome EC device. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Iec4b0226d1e98ddeb0f8ed8b89477fc4f453d221 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40513 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20ec/google/chromeec: Fill up SSDT for EC provided PS2 keyboardRajat Jain
Query the EC to get the top row layout, and if it provides one, generate the SSDT for the PS2 keyboard. Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I75d2eee32c82b9bee73436b08b5f615d1b388148 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40032 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-20 13:36:37 +0000