| Age | Commit message (Expand) | Author |
|---|---|---|
| 2013-05-10 | Drop prototype guarding for romcc | Stefan Reinauer |
| 2013-02-11 | Intel: Replace MSR 0xcd with MSR_FSB_FREQ | Patrick Georgi |
| 2013-02-09 | speedstep: Deduplicate some MSR identifiers | Patrick Georgi |
| 2012-11-05 | Overhaul speedstep code | Nico Huber |
| 2012-11-01 | Merge cpu/intel/acpi.h into cpu/intel/speedstep.h | Nico Huber |
| 2012-04-06 | Fixes and Sandybridge support for lapic cpu init | Stefan Reinauer |
| 2010-12-11 | factor out cpu power management base into a separate file. And fix a bug in | Stefan Reinauer |
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index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |