coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2014-08-15	intel/cpu: rename car.h to romstage.h	Aaron Durbin
2014-08-14	Intel: Add common header file for CAR setup	Edward O'Callaghan
2014-01-16	cpu/intel: Make all Intel CPUs load microcode from CBFS	Alexandru Gagniuc
2013-12-13	cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS	Alexandru Gagniuc
2013-05-10	Drop prototype guarding for romcc	Stefan Reinauer
2013-04-03	intel/microcode.h: Fix typo in comment: microcode	Paul Menzel
2013-03-19	intel microcode: split up microcode loading stages	Aaron Durbin
2013-02-11	Intel: Replace MSR 0xcd with MSR_FSB_FREQ	Patrick Georgi
2013-02-09	speedstep: Deduplicate some MSR identifiers	Patrick Georgi
2012-11-05	Overhaul speedstep code	Nico Huber
2012-11-01	Merge cpu/intel/acpi.h into cpu/intel/speedstep.h	Nico Huber
2012-09-05	buildsystem: Make CPU microcode updating more configurable	Alexandru Gagniuc
2012-07-24	Add code to read Intel microcode from CBFS	Vadim Bendebury
2012-07-02	Intel CPUs: execute microcode update only once per core	Kyösti Mälkki
2012-04-26	Revamp Intel microcode update code	Stefan Reinauer
2012-04-06	Fixes and Sandybridge support for lapic cpu init	Stefan Reinauer
2012-04-03	Add support for Intel Turbo Boost feature	Stefan Reinauer
2011-08-04	cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.	Keith Hui
2010-12-11	factor out cpu power management base into a separate file. And fix a bug in	Stefan Reinauer
2010-11-18	For completeness sake: License header.	Patrick Georgi
2010-11-17	Move Intel power management related defines to some central location.	Patrick Georgi
2009-01-20	fix compiler warnings (trivial)	Stefan Reinauer
2004-10-14	- Renamed cpu header files	Eric Biederman