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path: root/src/include/cpu
AgeCommit message (Expand)Author
2013-03-15Google Link: Add remaining code to support native graphicsRonald G. Minnich
2013-03-15haswell: reserve default SMRAM spaceAaron Durbin
2013-03-14x86: SMM Module SupportAaron Durbin
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2013-02-27smm: Update rev 0x30101 SMM revision save stateAaron Durbin
2013-02-18AMD Family12h: Fix warningsMartin Roth
2013-02-11Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi
2013-02-09speedstep: Deduplicate some MSR identifiersPatrick Georgi
2012-12-06Unify assembler function handlingStefan Reinauer
2012-11-20Unify use of bool config variablesStefan Reinauer
2012-11-14SMM: Avoid use of global variables in SMI handlerDuncan Laurie
2012-11-13Pass the CPU index as a parameter to startup.Ronald G. Minnich
2012-11-12Fix gcc-4.7 building problem.Han Shen
2012-11-05Overhaul speedstep codeNico Huber
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
2012-09-05buildsystem: Make CPU microcode updating more configurableAlexandru Gagniuc
2012-08-09AMD northbridge: copy TOP_MEM and TOP_MEM2 for distributionKyösti Mälkki
2012-08-09Synchronize rdtsc instructionsStefan Reinauer
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
2012-07-25SMM: rename tseg_fixup to tseg_relocate and exportDuncan Laurie
2012-07-24SMM: Fix state save map for sandybridge and TSEGDuncan Laurie
2012-07-24Add code to read Intel microcode from CBFSVadim Bendebury
2012-07-04Intel cpus: Extend cache to cover complete Flash DeviceKyösti Mälkki
2012-07-03AGESA F15 wrapper for Trinityzbao
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
2012-07-02Intel CPUs: execute microcode update only once per coreKyösti Mälkki
2012-05-24cbtypes.h: Unify cbtypes.h used in AMD board's codeVikram Narayanan
2012-05-08Clean up #ifsPatrick Georgi
2012-04-27SMM: unify mainboard APM command handlersStefan Reinauer
2012-04-27cpu/cpu.h: add ROMCC guardsStefan Reinauer
2012-04-26Revamp Intel microcode update codeStefan Reinauer
2012-04-25Replace cache control magic numbers with symbolsPatrick Georgi
2012-04-06Fixes and Sandybridge support for lapic cpu initStefan Reinauer
2012-04-04Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
2012-03-30Make MTRR min hole alignment 64MBDuncan Laurie
2012-03-30Add an option to keep the ROM cached after romstageStefan Reinauer
2012-03-29Add infrastructure for global data in the CAR phase of bootGabe Black
2012-03-16xchg is atomic with side-effectsPatrick Georgi
2012-03-08Unify Local APIC address definitionsPatrick Georgi
2012-02-16AGESA F15: AGESA family15 model 00-0fh cpu wrapperKerry Sheh
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
2011-11-01remove trailing whitespaceStefan Reinauer
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
2011-09-15Build warning fix for AMD Family 12efdesign98
2011-09-12Miscellaneous AMD F14 warning fixesefdesign98
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
2011-07-13Make AMD SMM SMP awareRudolf Marek
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