summaryrefslogtreecommitdiff
path: root/src/include/cpu
AgeCommit message (Collapse)Author
2014-10-19amd: rename model_fxx_powernow to powernow.Vladimir Serbinenko
Change-Id: Iee581183f9cd9f5fecd5604536b735f6a04a0f93 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7019 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
Placement of romstage stack in RAM was vulnerable for getting corrupted by decompressed ramstage. Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7096 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-17acpi_add_ssdt_pstates: Remove function.Vladimir Serbinenko
Nowhere in database p_state_num is set. So this whole function ends up being a noop. Moreover the offsets used by it are wrong with any optimizing iasl. Remove it in preparation of move to per-device ACPI. Change-Id: I1f1f9743565aa8f0b8fca472ad4cb6d7542fcecb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7012 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-08-30AMD Steppe Eagle: CPU files for new SoCBruce Griffith
Add the CPU files required to support the Steppe Eagle and Mullins models of Family 16h SoC processors from AMD. This CPU is based on the Jaguar core and is similar to Kabini. Change-Id: Ib48a3f03128f99a1242fe8c157e0e98feb53b1ea Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6679 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-15intel/cpu: rename car.h to romstage.hAaron Durbin
This header has nothing to do with cache-as-ram. Therefore, 'car' is the wrong term to use. It is about providing a prototype for *romstage*. Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6661 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-14Intel: Add common header file for CAR setupEdward O'Callaghan
When passing '-ffreestanding' the 'main' romstage.c may no longer necessarily be considered the entry point. From the C specification in 5.1.2.1 Freestanding environment; "In a freestanding environment (in which C program execution may take place without any benefit of an operating system), the name and type of the function called at program startup are implementation-defined." Clang complains about these being missing as Clang is somewhat more strict about the spec than GNU/GCC is. An advantage here is that a different entry-point type-signature shall now be warned about at compile time. Change-Id: I467001adabd47958c30c9a15e3248e42ed1151f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5872 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-17drivers/spi: Sanitize headers from preprocessor abuseEdward O'Callaghan
Continuing on from the rational given in: a173a62 Remove guarding #includes by CONFIG_FOO combinations Change-Id: I35c636ee7c0b106323b3e4b90629f7262750f8bd Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6114 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-30x86 MTRR: Drop unused return valueKyösti Mälkki
It was never well-defined what value this function should return. Change-Id: If84aff86e0b556591d7ad557842910a2dfcd3b46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6166 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-28AMD: Add common header file for CAR setupKyösti Mälkki
Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4683 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-16cpu/amd/agesa/family15tn: Add initial support for SMM modeAlexandru Gagniuc
This is the minimal setup needed to be able to execute SMI handlers. Only support for ASEG handlers is added, which should be sufficient for Trinity (up to 4 cores). There are a few hacks which need to be introduced in generic code in order to make this work properly, but these hacks are self-contained. They are a not a result of any special needs of this CPU, but rather from a poorly designed infrastructure. Comments are added to explain how such code could be refactored in the future. Change-Id: Iefd4ae17cf0206cae8848cadba3a12cbe3b2f8b6 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5493 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-03-20rmodules: use rmodtool to create rmodulesAaron Durbin
Start using the rmodtool for generating rmodules. rmodule_link() has been changed to create 2 rules: one for the passed in <name>, the other for creating <name>.rmod which is an ELF file in the format of an rmodule. Since the header is not compiled and linked together with an rmodule there needs to be a way of marking which symbol is the entry point. __rmodule_entry is the symbol used for knowing the entry point. There was a little churn in SMM modules to ensure an rmodule entry point symbol takes a single argument. Change-Id: Ie452ed866f6596bf13f137f5b832faa39f48d26e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5379 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-03-16Make POST device configurable.Idwer Vollering
Change-Id: If92b50ab3888518228d2d3b76f5c50c4aef968dd Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4561 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-02-25Remove CACHE_ROM.Vladimir Serbinenko
With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs depending on system configuration, hence screwing up I/O access and cache coherency in worst cases. CACHE_ROM requires the user to sanity check their boot output because the feature is brittle. The working configuration is dependent on I/O hole size, ram size, and chipset. Because of this the current implementation can leave a system configured in an inconsistent state leading to unexpected results such as poor performance and/or inconsistent cache-coherency Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5146 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-16x86: provide infrastructure to backup default SMM regionAaron Durbin
Certain CPUs require the default SMM region to be backed up on resume after a suspend. The reason is that in order to relocate the SMM region the default SMM region has to be used. As coreboot is unaware of how that memory is used it needs to be backed up. Therefore provide a common method for doing this. Change-Id: I65fe1317dc0b2203cb29118564fdba995770ffea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5216 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-11SMP: Add arch-agnostic boot_cpu()Kyösti Mälkki
We should not have x86 specific includes in lib/. Change-Id: I18fa9c8017d65c166ffd465038d71f35b30d6f3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5156 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-30x86: Add SMM helper functions to MP infrastructureAaron Durbin
In order for the cpu code to start SMM relocation 2 new functions are added to be shared: - void smm_initiate_relocation_parallel() - void smm_initiate_relocation() The both initiate an SMI on the currently running cpu. The 2 variants allow for parallel relocation or serialized relocation. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted rambi using these functions. Change-Id: I325777bac27e9a0efc3f54f7223c38310604c5a2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173982 Reviewed-on: http://review.coreboot.org/4891 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-30x86: add SMM save state for 0x0100 revisionAaron Durbin
The Bay Trail SMM save state revision is 0x0100. Add support for this save state area using the type named em64t100_smm_state_save_area_t. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted using this structure with forthcoming CLs. Change-Id: Iddd9498ab9fffcd865dae062526bda2ffcdccbce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173981 Reviewed-on: http://review.coreboot.org/4890 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-30x86: parallel MP initializationAaron Durbin
Provide a common entry point for bringing up the APs in parallel. This work is based off of the Haswell one which can be moved over to this in the future. The APs are brought up and have the BSP's MTRRs duplicated in their own MTRRs. Additionally, Microcode is loaded before enabling caching. However, the current microcode loading support assumes Intel's mechanism. The infrastructure provides a notion of a flight plan for the BSP and APs. This allows for flexibility in the order of operations for a given architecture/chip without providing any specific policy. Therefore, the chipset caller can provide the order that is required. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted on rambi with baytrail specific patches. Change-Id: I0539047a1b24c13ef278695737cdba3b9344c820 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173703 Reviewed-on: http://review.coreboot.org/4888 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-28x86: add common definitions for control registersAaron Durbin
The access to control registers were scattered about. Provide a single header file to provide the correct access function and definitions. BUG=chrome-os-partner:22991 BRANCH=None TEST=Built and booted using this infrastructure. Also objdump'd the assembly to ensure consistency (objdump -d -r -S | grep xmm). Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172641 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4873 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28x86/mtrr: don't assume size of ROM cached during CAR modeAaron Durbin
Romstage and ramstage can use 2 different values for the amount of ROM to cache just under 4GiB in the address space. Don't assume a cpu's romstage caching policy for the ROM. Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4846 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-28x86: include header to define types in useAaron Durbin
The tsc header is using u32 w/o including the file with defines it. Change-Id: I9fcad882d25e93b4c0032b32abd2432b0169a068 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4843 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-23Multiboot: remove multiboot tables generation.Vladimir Serbinenko
GRUB2-as-payload doesn't use them. Libpayload can live with just coreboot tables if loaded as payload. memtest86+ can use them but is buggy with them. Solaris needs a huge boot archive not supported by coreboot and too big to fit in flash (dozens of megabytes). All-in-all looks like no users are left for this. Change-Id: Id92f73be5a397db80f5b0132ee57c37ee6eeb563 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4628 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-16cpu/intel: Make all Intel CPUs load microcode from CBFSAlexandru Gagniuc
The sequence to inject microcode updates is virtually the same for all Intel CPUs. The same function is used to inject the update in both CBFS and hardcoded cases, and in both of these cases, the microcode resides in the ROM. This should be a safe change across the board. The function which loaded compiled-in microcode is also removed here in order to prevent it from being used in the future. The dummy terminators from microcode need to be removed if this change is to work when generating microcode from several microcode_blob.c files, as is the case for older socketed CPUs. Removal of dummy terminators is done in a subsequent patch. Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4495 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be set with values that are not power of 2. The region programmed as WB cacheable will include all of ROM_SIZE. Side-effects to consider: Memory region below flash may be tagged WRPROT cacheable. As an example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB. Since this can overlap CAR, we add an explicit test and fail on compile should this happen. To work around this problem, one needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and define a smaller region for WB cache. With this change flash regions outside CBFS are also tagged WRPROT cacheable. This covers IFD and ME and sections ChromeOS may use. Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4625 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-06cpu/cpu.h: Allow compiling with __SIMPLE_DEVICE__Vladimir Serbinenko
Change-Id: I14a2ac47198be6359b4f10b38f1cf86c9917d67e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4602 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-12-26AMD boards (non-AGESA): Cleanup earlymtrr.c includesKyösti Mälkki
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4523 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-21lynxpoint: Route all USB ports to XHCI in finalize stepDuncan Laurie
This commit adds a new Kconfig option for the LynxPoint southbridge that will have coreboot route all of the USB ports to the XHCI controller in the finalize step (i.e. after the bootloader) and disable the EHCI controller(s). Additionally when doing this the XHCI USB3 ports need to be put into an expected state on resume in order to make the kernel state machine happy. Part of this could also be done in depthcharge but there are also some resume-time steps required so it makes sense to keep it all together in coreboot. This can theoretically save ~100mW at runtime. Verify that the EHCI controller is not found in Linux and that booting from USB still works. Change-Id: I3ddfecc0ab12a4302e6034ea8d13ccd8ea2a655d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63802 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4407 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-13cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFSAlexandru Gagniuc
CPU_MICROCODE_IN_CBFS was designed to mean that loading microcode updates from a CBFS file is supported, however, the name implies that microcode is present in CBFS. This has recently caused confusion both with contributions from Google, as well as SAGE. Rename this option to SUPPORT_CPU_UCODE_IN_CBFS in order to make it clearer that what is meant is "hey, the code we have for this CPU supports loading microcode updates from CBFS", and prevent further confusion. Change-Id: I394555f690b5ab4cac6fbd3ddbcb740ab1138339 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4482 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2013-12-09AMD boards: Fix includes for microcode updatesKyösti Mälkki
No ROMCC involved, no need to include .c files in romstage.c. Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4501 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-24smi: Update mainboard_smi_gpi() to have 32bit argumentDuncan Laurie
With the LynxPoint chipset there are more than 16 possible GPIOs that can trigger an SMI so we need a mainboard handler that can support this. There are only a handful of users of this function so just change them all to use the new prototype. Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49530 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4145 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-10-13Rename cpu/x86/car.h to arch/early_variables.hStefan Reinauer
and add an ARMv7 version. Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156 Signed-off-by: Stefan Reinauer <reinauer@google.com> [km: rebased fa004acf8 from chromium git] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3939 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-09-21CBMEM: Always select CAR_MIGRATIONKyösti Mälkki
If romstage does not make cbmem_initialize() call, linker should optimize the code for CAR migration away. This simplifies design of CBMEM console by a considerable amount. As console buffer is now migrated within cbmem_initialize() call there is no longer need for cbmemc_reinit() call made at end of romstage. Change-Id: I8675ecaafb641fa02675e9ba3f374caa8e240f1d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3916 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-15Include boot_cpu.c for romstage buildsKyösti Mälkki
ROMCC boards were left unmodified. Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-05AMD Kabini: Add CPU AGESA wrapper for new AMD processor familySiyuan Wang
Change-Id: I4a1d2118aeb2895f3c2acea5e792fbd69c855156 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Mike Loptien <mike.loptien@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3781 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-07-11include: Fix spellingMartin Roth
Change-Id: Iadc813bc8208278996b2b1aa20cfb156ec06fac9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3755 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-03include/cpu/amd: Align `CPU_ID_EXT_FEATURES_MSR` with other definesPaul Menzel
Probably due to different (character) widths for a tab, sometimes only one tab was used for aligning the define `CPU_ID_EXT_FEATURES_MSR`. For the “correct” alignment, that means where a tab is eight characters, two tabs are necessary. Change it accordingly. Change-Id: I450a7796dc00b934b5a6bab8642db04a27f69f4b Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3263 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-05-25Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`Ronald G. Minnich
multiply_to_tsc was being copied everywhere, which is bad practice. Put it in the tsc.h include file where it belongs. Delete the copies of it. Per secunet, no copyright notice is needed. This might be a good time to get a copyright notice into tsc.h anyway. Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3242 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-16x86: add cache-as-ram migration optionAaron Durbin
There are some boards that do a significant amount of work after cache-as-ram is torn down but before ramstage is loaded. For example, using vboot to verify the ramstage is one such operation. However, there are pieces of code that are executed that reference global variables that are linked in the cache-as-ram region. If those variables are referenced after cache-as-ram is torn down then the values observed will most likely be incorrect. Therefore provide a Kconfig option to select cache-as-ram migration to memory using cbmem. This option is named CAR_MIGRATION. When enabled, the address of cache-as-ram variables may be obtained dynamically. Additionally, when cache-as-ram migration occurs the cache-as-ram data region for global variables is copied into cbmem. There are also automatic callbacks for other modules to perform their own migration, if necessary. Change-Id: I2e77219647c2bd2b1aa845b262be3b2543f1fcb7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3232 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-11Make early x86 POST codes written to IO port optionalMartin Roth
This continues the work done in patch 6b908d08ab http://review.coreboot.org/#/c/1685/ and makes the early x86 post codes follow the same options. Change-Id: Idf0c17b27b3516e79a9a53048bc203245f7c18ff Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3237 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10Get rid of a number of __GNUC__ checksStefan Reinauer
In the process of streamlining coreboot code and getting rid of unneeded ifdefs, drop a number of unneeded checks for the GNU C compiler. This also cleans up x86emu/types.h significantly by dropping all the duplicate types in there. Change-Id: I0bf289e149ed02e5170751c101adc335b849a410 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3226 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-10Drop prototype guarding for romccStefan Reinauer
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1] made romcc not choke on function prototypes anymore. This allows us to get rid of a lot of ifdefs guarding __ROMCC__ . [1] http://review.coreboot.org/2424 Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3216 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-08x86: use asmlinkage macro for smm_handler_tAaron Durbin
The smm_handler_t type was added before the introduction of the asmlinkage macro. Now that asmlinkage is available use it. Change-Id: I85ec72cf958bf4b77513a85faf6d300c781af603 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3215 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-05-07x86: add TSC_CONSTANT_RATE optionAaron Durbin
Some boards use the local apic for udelay(), but they also provide their own implementation of udelay() for SMM. The reason for using the local apic for udelay() in ramstage is to not have to pay the penalty of calibrating the TSC frequency. Therefore provide a TSC_CONSTANT_RATE option to indicate that TSC calibration is not needed. Instead rely on the presence of a tsc_freq_mhz() function provided by the cpu/board. Additionally, assume that if TSC_CONSTANT_RATE is selected the udelay() function in SMM will be the tsc. Change-Id: I1629c2fbe3431772b4e80495160584fb6f599e9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3168 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01x86: use boot state callbacks to disable rom cacheAaron Durbin
On x86 systems there is a concept of cachings the ROM. However, the typical policy is that the boot cpu is the only one with it enabled. In order to ensure the MTRRs are the same across cores the rom cache needs to be disabled prior to OS resume or boot handoff. Therefore, utilize the boot state callbacks to schedule the disabling of the ROM cache at the ramstage exit points. Change-Id: I4da5886d9f1cf4c6af2f09bb909f0d0f0faa4e62 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3138 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-12Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region"Nico Huber
This reverts commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5: commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5 Author: Patrick Georgi <patrick.georgi@secunet.com> Date: Tue Apr 9 15:41:23 2013 +0200 siemens/sitemp_g1p1: Make ACPI report the right mmconf region ACPI reported the entire space between top-of-memory and some (relatively) arbitrary limit as useful for MMIO. Unfortunately the HyperTransport configuration disagreed. Make them match up. Other boards are not affected since they don't report any region for that purpose at all (it seems). Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> It sneaked in without it's dependencies and, therefore, broke the build for all amdk8 targets. Paul Menzel already commented on the issue in [1]. It also doesn't look like the dependencies would be pulled soon [2]. [1] http://review.coreboot.org/#/c/3047/ [2] http://review.coreboot.org/#/c/2662/ Change-Id: Ica89563aae4af3f0f35cacfe37fb608782329523 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3063 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-04-10siemens/sitemp_g1p1: Make ACPI report the right mmconf regionPatrick Georgi
ACPI reported the entire space between top-of-memory and some (relatively) arbitrary limit as useful for MMIO. Unfortunately the HyperTransport configuration disagreed. Make them match up. Other boards are not affected since they don't report any region for that purpose at all (it seems). Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-05mtrr: add rom caching comment about hyperthreadsAaron Durbin
Explicitly call out the effects of hyperthreads running the MTRR code and its impact on the enablement of ROM caching. Change-Id: I14b8f3fdc112340b8f483f2e554c5680576a8a7c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3018 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-04AMD: Drop six copies of wrmsr_amd and rdmsr_amdKyösti Mälkki
Based on comments in cpu/x86/msr.h for wrmsr/rdmsr, and for symmetry, I have added __attribute__((always_inline)) for these. Change-Id: Ia0a34c15241f9fbc8c78763386028ddcbe6690b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2898 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-03intel/microcode.h: Fix typo in comment: micr*o*codePaul Menzel
Introduced in commit »intel microcode: split up microcode loading stages« (98ffb426) [1]. [1] http://review.coreboot.org/2778 Change-Id: I626508b10f3998b43aaabd49853090b36f5d3eb0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2992 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2013-04-01boot: add disable_cache_rom() functionAaron Durbin
On certain architectures such as x86 the bootstrap processor does most of the work. When CACHE_ROM is employed it's appropriate to ensure that the caching enablement of the ROM is disabled so that the caching settings are symmetric before booting the payload or OS. Tested this on an x86 machine that turned on ROM caching. Linux did not complain about asymmetric MTRR settings nor did the ROM show up as cached in the MTRR settings. Change-Id: Ia32ff9fdb1608667a0e9a5f23b9c8af27d589047 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2980 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 10:24:00 +0000