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2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15treewide: Replace uses of "Nehalem"Angel Pons
The code in coreboot is actually for the Arrandale processors, which are a MCM (Multi-Chip Module) with two different dies: - Hillel: 32nm Westmere dual-core CPU - Ironlake: 45nm northbridge with integrated graphics This has nothing to do with the older, single-die Nehalem processors. Therefore, replace the references to Nehalem with the correct names. Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07cpu/x86/smm: Add smm_size to relocatable smmstubArthur Heymans
To mitigate against sinkhole in software which is required on pre-sandybridge hardware, the smm entry point needs to check if the LAPIC base is between smbase and smbase + smmsize. The size needs to be available early so add them to the relocatable module parameters. When the smmstub is used to relocate SMM the default SMM size 0x10000 is provided. On the permanent handler the size provided by get_smm_info() is used. Change-Id: I0df6e51bcba284350f1c849ef3d012860757544b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04include/cpu/amd: Drop unused filesElyes HAOUAS
Change-Id: Iff14250e52854d598967cfd3cbc98061be06e581 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38055 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-21security/intel/stm: Check for processor STM supportEugene Myers
Check to ensure that dual monitor mode is supported on the current processor. Dual monitor mode is normally supported on any Intel x86 processor that has VTx support. The STM is a hypervisor that executes in SMM dual monitor mode. This check should fail only in the rare case were dual monitor mode is disabled. If the check fails, then the STM will not be initialized by coreboot. Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: I518bb2aa1bdec94b5b6d5e991d7575257f3dc6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-05security/intel/stm: Add STM supportEugene Myers
This update is a combination of all four of the patches so that the commit can be done without breaking parts of coreboot. This possible breakage is because of the cross-dependencies between the original separate patches would cause failure because of data structure changes. security/intel/stm This directory contains the functions that check and move the STM to the MSEG, create its page tables, and create the BIOS resource list. The STM page tables is a six page region located in the MSEG and are pointed to by the CR3 Offset field in the MSEG header. The initial page tables will identity map all memory between 0-4G. The STM starts in IA32e mode, which requires page tables to exist at startup. The BIOS resource list defines the resources that the SMI Handler is allowed to access. This includes the SMM memory area where the SMI handler resides and other resources such as I/O devices. The STM uses the BIOS resource list to restrict the SMI handler's accesses. The BIOS resource list is currently located in the same area as the SMI handler. This location is shown in the comment section before smm_load_module in smm_module_loader.c Note: The files within security/intel/stm come directly from their Tianocore counterparts. Unnecessary code has been removed and the remaining code has been converted to meet coreboot coding requirements. For more information see: SMI Transfer Monitor (STM) User Guide, Intel Corp., August 2015, Rev 1.0, can be found at firmware.intel.com include/cpu/x86: Addtions to include/cpu/x86 for STM support. cpu/x86: STM Set up - The STM needs to be loaded into the MSEG during BIOS initialization and the SMM Monitor Control MSR be set to indicate that an STM is in the system. cpu/x86/smm: SMI module loader modifications needed to set up the SMM descriptors used by the STM during its initialization Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-12-19src: Use '#include <smp/node.h>' when appropriateElyes HAOUAS
Change-Id: Icdd6b49751763ef0edd4c57e855cc1d042dc6d4d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19Drop ROMCC code and header guardsArthur Heymans
Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-18Revert "include/cpu/x86: Add STM Support"Aaron Durbin
This reverts commit 297b6b862a724de70abf33f681f63b6a3d84c24b. Reason for revert: breaks smm. No code is using these fields. Original patch incomplete. Change-Id: I6acf15dc9d77ed8a83b98f086f2a0b306c584a9b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37096 Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-18include/cpu/x86: Add STM SupportEugene D. Myers
Addtions to include/cpu/x86 include for STM support. Change-Id: I2b8e68b2928aefc7996b6a9560c52f71c7c0e1d0 Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-11-30AGESA,binaryPI: Add compatibility wrapper for romstage entryKyösti Mälkki
This simplifies transition and reviews towards C environment bootblock by allowing single cache_as_ram.S file to be used. Change-Id: I231972982e5ca6d0c08437693edf926b0eaf9ee1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37352 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30AGESA,binaryPI: Fix stack location on entry to romstageMichał Żygowski
For BSP CPU, set up stack location to match the symbol from car.ld. For AP CPUs the stack is located outside _car_region and is currently not accounted for in the linker scripts. Change-Id: I0ec84ae4e73ecca5034f799cdc2a5c1056ad8b74 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-30AGESA,binaryPI: Split romstage_main() to BSP and AP partsKyösti Mälkki
BSP and AP have two distinct execution paths for romstage. Change-Id: Id013b165f1345509fe6b74cef2bf8c3b420f84a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30binaryPI: Clean leftover romstage prototypeKyösti Mälkki
Change-Id: Ie9e7a88f1f8dce967772e7c5ecf4aea971bb1c3f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37346 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27AGESA,binaryPI: Remove early_all_cores()Kyösti Mälkki
This was implemented to make sure it gets called before attempting any PCI MMIO access. Now that we have one central romstage_main() implementation this extra precaution is no longer useful. Change-Id: I09b24da827e00d7a9ba0a51d5eef36f174b893a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-27binaryPI: Drop BINARYPI_LEGACY_WRAPPER supportKyösti Mälkki
Drop all the sources that were guarded with this. Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/19275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-27amdfam10: Clean leftover prototypesKyösti Mälkki
Change-Id: Ic3278cb1148c34284aba59f6f588713b683ca90b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-22cpu/intel/smm: Drop em64t save stateArthur Heymans
This save state is just plainly wrong in many regards and em64t100 should be used. Checked with a model 0x17 core2 CPU. Change-Id: I4d89691e87c91dd12b34a44b74849b18b4ac5369 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-22intel/smm: Provide common smm_relocation_paramsKyösti Mälkki
Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-08arch/x86: Drop some __SMM__ guardsKyösti Mälkki
Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-04cpu/intel/em64t101: Add Nehalem to compatibility listArthur Heymans
Change-Id: I15a1c824b92e18f9963c60659ead92c988d1239b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-03cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki
The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-31cpu/x86: make set_msr_bit publicly availableMichael Niewöhner
Haswell and model_2065 implement a static set_msr_bit helper which should be publicly available instead. Move it to cpu/x86. Change-Id: I68b314c917f15fc6e5351de1c539d5a3ae646df8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36338 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-01cpu/intel/common: Move intel_ht_sibling() to common folderPatrick Rudolph
Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28cpu,device/: Remove some __SIMPLE_DEVICE__ and __ROMCC__ useKyösti Mälkki
Change-Id: I62d7450c8e83eec7bf4ad5d0709269a132fd0499 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-19cpu/x86/lapic: Refactor timer_fsb()Kyösti Mälkki
Common apic_timer code in cpu/x86 should not depend on intel header files. Change-Id: Ib099921d4b8e561daea47219385762bb00fc4548 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34091 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14arch/x86: Replace some __PRE_RAM__ useKyösti Mälkki
Change-Id: I4d8db430f8cd0bf0f161fc5cef052f153e59e2bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35390 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14cpu/x86: Drop lapic_remote_read()Kyösti Mälkki
Unused and declaration conflicts with the one amdfam10-15 uses in romstage. Change-Id: Icd454431285b7c423a4f78d2a0085497d052adc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35394 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28intel/smm/gen1: Use smm_subregion()Kyösti Mälkki
Change-Id: I371ed41f485b3143e47f091681198d6674928897 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34740 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26amdfam10: Remove use of __PRE_RAM__Kyösti Mälkki
Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-22arch/x86: Add <arch/romstage.h>Kyösti Mälkki
Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20device/oprom: Drop unnecessary AMD headersKyösti Mälkki
Change-Id: I548dfa053f195b1ea87568240bf0041bb193d825 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-15intel/smm: Define struct ied_header just onceKyösti Mälkki
Change-Id: I6fc083aa30d05c11c1b6db7b3facacf5ae857c92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15soc/intel: Rename some SMM support functionsKyösti Mälkki
Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15intel/smm/gen1: Rename header fileKyösti Mälkki
Change-Id: I258fccc5e1db0bedb641c8af8cb9727954d4d7c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15soc/*: mp_run_on_all_cpus: Remove configurable timeoutPatrick Rudolph
Some timeouts given were too small when serial console is enabled due to its spinlock making code runtime worse with every AP present. In addition we usually don't know how long specific code runs and how long ago it was sent to the APs. Remove the timeout argument from mp_run_on_all_cpus and instead wait up to 1 second, to prevent possible crashing of secondary APs still processing the old job. Tested on Supermicro X11SSH-TF. Change-Id: I456be647b159f7a2ea7d94986a24424e56dcc8c4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-15cpu/x86/smm: Promote smm_memory_map()Kyösti Mälkki
Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15cpu/intel: Refactor platform_enter_postcar()Kyösti Mälkki
There are benefits in placing the postcar_frame structure in .bss and returning control to romstage_main(). Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-13cpu/x86: Hide smm_save_state_area_t typedefKyösti Mälkki
We mostly discourage typedefs for structs. Hide smm_save_state_area_t in the single file that still uses it. Change-Id: I163322deab58126cc66d416987eaf7dca9ce8220 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-13cpu/x86: Change old-style SMI handler prototypesKyösti Mälkki
Change-Id: Ic1e3cae5298997b552020b78e6ff56d60cf22036 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34821 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13cpu/x86: Move some SMM function declarationsKyösti Mälkki
Change-Id: I9a4e57f8fd032f2824eab0e5b59d635710e3e24b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-13cpu/x86: Separate save_state struct headersKyösti Mälkki
Any platform should need just one of these. Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Change smm_subregion() prototypeKyösti Mälkki
Do this to avoid some amount of explicit typecasting that would be required otherwise. Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07soc/amd: Rename smm_region_info() to smm_region()Kyösti Mälkki
Change-Id: I361fb0e02fd0bd92bb1e13fe84c898a1ac85aa40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34703 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki
No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-11cpu/x86: Declare smi_release_lock() staticKyösti Mälkki
Change-Id: I535ff1b16b1fa7c3c8c14b2be7eac32568f16077 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34194 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07cpu/x86: Fix MSR_PLATFORM_INFO definitionKyösti Mälkki
While common to many Intel CPUs, this is not an architectural MSR that should be globally defined for all x86. Change-Id: Ibeed022dc2ba2e90f71511f9bd2640a7cafa5292 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Guckian
2019-07-07include/cpu/x86/mtrr: Fix return typeElyes HAOUAS
fms() and fls() returns an 'unsigned int'. Change-Id: Ia328e1e5a79c2e7606961bb1b68c01db6b77da21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33817 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 07:30:39 +0000