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AgeCommit message (Expand)Author
2012-05-08Clean up #ifsPatrick Georgi
2012-04-27SMM: unify mainboard APM command handlersStefan Reinauer
2012-04-27cpu/cpu.h: add ROMCC guardsStefan Reinauer
2012-04-26Revamp Intel microcode update codeStefan Reinauer
2012-04-25Replace cache control magic numbers with symbolsPatrick Georgi
2012-04-06Fixes and Sandybridge support for lapic cpu initStefan Reinauer
2012-04-04Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
2012-03-30Make MTRR min hole alignment 64MBDuncan Laurie
2012-03-30Add an option to keep the ROM cached after romstageStefan Reinauer
2012-03-29Add infrastructure for global data in the CAR phase of bootGabe Black
2012-03-16xchg is atomic with side-effectsPatrick Georgi
2012-03-08Unify Local APIC address definitionsPatrick Georgi
2012-02-16AGESA F15: AGESA family15 model 00-0fh cpu wrapperKerry Sheh
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
2011-11-01remove trailing whitespaceStefan Reinauer
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
2011-09-15Build warning fix for AMD Family 12efdesign98
2011-09-12Miscellaneous AMD F14 warning fixesefdesign98
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
2011-07-13Make AMD SMM SMP awareRudolf Marek
2011-06-28Addition of Family12/SB900 wrapper codeefdesign98
2011-06-28SMM: add guard and include types.h in cpu/x86/smm.hSven Schnelle
2011-06-15SMM: don't overwrite SMM memory on resumeSven Schnelle
2011-06-07SMM: add defines for APM_CNT registerSven Schnelle
2011-06-06SMM: add mainboard_apm_cnt() callbackSven Schnelle
2011-05-15Cosmetic cleanup.Scott Duplichan
2011-04-21more ifdef -> if fixesStefan Reinauer
2011-04-21some ifdef --> if fixesStefan Reinauer
2011-04-11Unify use of post_codeAlexandru Gagniuc
2011-04-10In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.Stefan Reinauer
2011-02-14I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347.Frank Vibrans
2011-01-19Revert r5902 to make code more readable again. At least three people like toStefan Reinauer
2011-01-19Now that the VIA code is run above 1Meg (like other boards), it shouldKevin O'Connor
2010-12-29-Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)Nils Jacobs
2010-12-26Replace Geode GX2 MSR addresses for GLCP on GLIU1 with namesNils Jacobs
2010-12-26Clean up Geode GX2 comments, whitespace and coding style. Trivial.Nils Jacobs
2010-12-18SMM for AMD K8 Part 1/2Stefan Reinauer
2010-12-17guard against the case that CONFIG_WAIT_BEFORE_CPUS_INIT is not defined at all.Stefan Reinauer
2010-12-11factor out cpu power management base into a separate file. And fix a bug inStefan Reinauer
2010-12-08second round name simplification. drop the <component>_ prefix.stepan
2010-11-18For completeness sake: License header.Patrick Georgi
2010-11-17Move Intel power management related defines to some central location.Patrick Georgi
2010-11-13MTRR related improvements for AMD family 10h and family 0Fh systemsScott Duplichan
2010-11-01Change Geode GX2 to use the auto DRAM detect code from Geode LX.Nils Jacobs
2010-11-01GX2: Clean up some white space and comments.Nils Jacobs
2010-10-12Reduce duplicate definition in CAR code.Warren Turkal
2010-10-01Factor out common CAR asm snippets.Uwe Hermann
2010-10-01CAR simplifications, typos, readability improvements (trivial).Uwe Hermann
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