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2009-04-01Drop CONFIG_CHIP_NAME. Those config statements in Config.lb shouldStefan Reinauer
be used unconditionally, and the names don't hurt. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13This, ladies and gentlement, is commit #4000.Stefan Reinauer
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few include files and missing prototypes. Also, fix up the Config-abuild.lb files to properly work for cross compiling. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06Fix mmconf (PCIe memory mapped config space access) support in v2. It wasStefan Reinauer
horribly broken and thus never used by any platform. This needs to get straightened out so current chipsets drivers can use the full feature set. Create wrapper functions similar to the io pci config space ones. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3Stefan Reinauer
a long time ago. This will make it easier to port v2 boards forward to v3 at some point (and other things) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18This patch gets rid of all the implicit definition warnings for serengeti ↵Myles Watson
except get_nodes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31Revert i945/ICH7 PCI IDs to be hard-coded numbers instead of #defines.Uwe Hermann
Build-tested on kontron_986lcd_m. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29i945/ICH7: Use #defines from pci_ids.h (trivial).Uwe Hermann
Build-tested with the kontron/986lcd-m target. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for the Intel ICH7 southbridge.Stefan Reinauer
This includes an early SMI handler. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-13Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.Uwe Hermann
Build-tested with the AMD dbm690t board. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-05This patch adds support for the VIA VT8237S south bridge. The VT8237R ↵Rudolf Marek
programming remains unchanged (tested on mine desktop) except of reverting the small change introduced by Bari (gpio/inta setup reg 0x5b). This should go for some board specific file. The change would broke at least mine board. But seems to be needed for jakllsch. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Bari Ari <bari@onelabs.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25This patch adds PCI device IDs for the Intel EP80579 Integrated Processor,Ed Swierk
and renames some existing macros for clarity. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20Following patch adds K8M890 support. It initializes the AGP and graphics UMA.Rudolf Marek
The V-link setup and HT bridge is redone, because VT8237A has it in another device. So far following combination of chipsets should now work: K8T890CE + VT8237R K8M890(CE) + VT8237R VIA PC1 brige moved to NB code (vt8237r_bridge.c -> k8t890_bridge.c) and notes about K8M890 support were added. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16oops. sorry, wrong checkin. This patch backs out r3155 and instead contains theEd Swierk
code it should have contained. This patch updates the PCI IDs for Intel 3100 devices. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-21Add support for the Via CN700 with a C7 CPU and DDR2 RAM. Only a single DIMM isCorey Osgood
working for now, and more work is needed for it to be fully dynamic. However, just about any 128MB-512MB DIMM should work. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-01 This patch fixes the decoding of the IO address range 0x0820->0x0827 into theFlorentin Demetrescu
LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI interface of the IT8716 SIO chip. Changes : 1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some functions of a PNP device can have more than 12 resources (ex the GPIO function of IT8716f), in which case one could have an "array overflow" inside the device structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at device init time..) 2) - define resource masks for the GPIO function in src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO ranges which are set into the LPC bridge of the SB are very strange (f.ex.: 0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching by the init code 3) - enable the flash SPI interface into src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource into the GPIO function). I know that this is problematic because not all m57sli boards are SPI, but .. do anyone have a better idea how to handle this?.. Signed-off-by: Florentin Demetrescu <echelon@free.fr> I (Ward) have verified your patch on a rev2 of this board (it works!) as well as on a rev1 (plcc). It does not affect flashing on rev1 nor have any averse side effects that I noticed, so I think this patch should go in. Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Rename almost all occurences of LinuxBIOS to coreboot. Stefan Reinauer
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-28Add Intel 3100 integrated northbridge/southbridge/superio PCI IDs.Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29Restructure/rename/comment a few 82371XX-related PCI IDs (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14* Maintaining SiS south bridge device IDs.Morgan Tsai
* Strip unnecessary driver modules. Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-07Add PCI IDs for most Intel southbridges of the 82801 seriesUwe Hermann
(ICH/ICH0 up to the ICH9 family) in preparation for further code improvements for the i82801xx southbridge code. Small fixes in the 6300ESB PCI IDs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-04Restructure the PCI IDs list for the ICH* chipsets from ICH/ICH0 up toUwe Hermann
ICH5/ICH5R (more to follow) in preparation of further 82801xx improvements. Use human-readable names for the PCI ID #defines. Rename *_ISA to *_LPC as per datasheet. The 82801DBM only has 3 (not 4) USB devices, looks like a copy-paste error. The fixes in southbridge code are only to keep the build working for now, any real improvements will only go into the 82801xx code in future. This is abuild-tested so it shouldn't break anything. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-021. vgabios removed, will go to extra repositoryMorgan Tsai
2. Rename sisnb.c to sis761.c 3. Delete many mis-definition for sis device in src/include/device/pci_ids.h 4. Trim trailing spaces for all files Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30Add support for the VIA VT8237R southbridge.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: <corey.osgood@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-22Add SiS device IDs for further update.Morgan Tsai
Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29Drop duplicate 82371AB device IDs (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29Intel 82371EB: Add IDE init support.Uwe Hermann
In a mainboard's Config.lb file you can configure whether the primary and/or secondary IDE interfaces shall be enabled. Also, various fixups in the rest of the southbridge code, most notably the early SMBus code, plus some documentation improvements. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey_osgood@verizon.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This patch updates the PCI ID of the Geode IDE device to include the revision.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch re-implements support for the CS5536 companion chip for theMarc Jones
AMD GX and LX processors. This aguments the previous code, which was very specific to the OLPC platform with general purpose support and better integration with the VSA and CPUs. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01This patch adds the MCP55 PCI IDs (without which the southbridge codeEd Swierk
won't compile), and breaks an unnecessary dependency on the usbdebug code. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04AMD Rev F supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-18fix old bug in the src/devices/pci_device.c Ronald G. Minnich
add devices for the lx and artecgroup/dbe61 point artecgroup at cs5536_lx as it is so different. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-28This patch adds support for the AMD LX cpu. Ron Minnich
There is one global change to pci_ids.h. The rest are changes for LX. I ran abuild and it is ok. Not all artec design changes are included as some of them would adversely affect other mainboards. Indrek will need to test. Signed-off-by: Ron Minnich Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec design. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20boot to kernelLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-28added GX2 idsRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-041203_hcdn.diff: Stefan Reinauer
store every HT device unit id base and pass those info to acpi https://openbios.org/roundup/linuxbios/issue46 Note: This version drops the two scripts a and c and creates the dsdt on the fly from Config.lb using makerule git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-02backing out pci device renamesStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-021201_ht_bus0_dev0_fidvid_core.diffStefan Reinauer
https://openbios.org/roundup/linuxbios/issue41 Lord have mercy upon us. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-26- Apply 11_24_a_s1_core.diff fromStefan Reinauer
https://openbios.org/roundup/linuxbios/issue24 - fix up for via epia-m git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-22EPIA-M fixupRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14Rename Intel 82801CA constants.Steven J. Magnani
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-08-08Fix up the VT8623 northbridge support.Jonathan McDowell
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08eric patchYinghai Lu
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-30arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> Nvidia Ck804 support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-10arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> pci_rom.h smbus device parent device print git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-4arch import user (historical)
Creator: Eric Biederman <ebiederman@lnxi.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-18class code reverseYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-13onboard pci_romYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-13onboard pci_romYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-10added PCI expansion ROM support,Li-Ta Lo
works for some ATI and Nvidia AGP cards now. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-27now rom_address is one of the resourcesLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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