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2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: add PCI id supportAaron Durbin
In order for coreboot to assign resources properly the pci drivers need to have th proper device ids. Add the host controller and the LPC device ids for Lynx Point. Resource assignment works correctly now w/o odd behavior because of conflicts. Change-Id: Id33b3676616fb0c428d84e5fe5c6b8a7cc5fbb62 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2638 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-11pci.h: Drop unused `mainboard_pci_subsystem*` prototypesPatrick Georgi
We used to allow mainboards to override subsystems using mainboard_pci_subsystem_vendor_id and mainboard_pci_subsystem_device_id. Mechanisms have changed and the only occurrence of these names is in the header. Change-Id: Ic2ab13201a2740c98868fdf580140b7758b62263 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2625 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-06replace uchar and uint with standard types in generic i2c headerDavid Hendricks
Change-Id: Ie72985bb5291bcef2e837a2f4f2ec929a0c086ce Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2290 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-29import i2c header from u-bootDavid Hendricks
This just imports a header. We may wish to modify the i2c interface and/or unify it with the smbus interface we currently have. Change-Id: I314f3aef62be936456c6c3e164a3db2c473b8792 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2079 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27Add initialization hook for chipsNico Huber
Add an init() function to the chip_operations which will be called before bus enumeration. This allows to disable unused devices before they get enumerated. Change-Id: I63dd9cbfc7b5995ccafb7bf7a81dc71fc67906a0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1623 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
Compose the name from Kconfig strings instead. As the field is for debug print use only, a minor change in the output should do no harm. The strings no longer include word "Mainboard". Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06Add name field for deviceKyösti Mälkki
The constant field "name" in chip_operations is common to multiple different devices within a chip and cannot reflect the actual device as found on the platform. The intention is that a driver sets dev->name as part of the device enumeration sequence with the detected hardware type and revision. The field is for debug print use only. Change-Id: Ib7bf90ba3c618ad0cb715d80d6a937ceaae0adcf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-29Drop get_smbios_data from chip_operationsKyösti Mälkki
We only want to add data once per device. Using the one in chip_operations is not very usable anyway, as different devices under the same chip directory would need to output entirely different sets of data. Change-Id: I96690c4c699667343ebef44a7f3de1f974cf6d6d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1492 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2012-10-27Take care of NULL chip_ops->nameKyösti Mälkki
Change-Id: Ic44915cdb07e0d87962eff0744acefce2a4845a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1626 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-08-27Drop unused ISA Pnp definitionsKyösti Mälkki
These declarations were never or no longer used. Change-Id: Icdbfc0838d5021ea02ab031b643b3fe6361b39b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1489 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-27AMD northbridges: factor out CPU allocationKyösti Mälkki
Factor CPU allocation out of AMD northbridge codes. As CPU topology information is required for generation of certain ACPI tables, make this code globally available. For AMDK8 and AMDFAM10 northbridge, there is a possible case of BSP CPU with lapicid!=0. We do not want to leave the lapic 0 from devicetree unused, so always use that node for BSP CPU. Change-Id: I8b1e73ed5b20b314f71dfd69a7b781ac05aea120 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1418 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-08Fix SMBIOS generationStefan Reinauer
Dropping mainboard's chip.h broke execution of the mainboard's enable function and the addition of mainboard specific smbios tables. The former was fixed by Kyosti in http://review.coreboot.org/1374 This patch fixes the breakage in static.c and also backs out a small portion of Kyosti's patch (because it's not needed anymore) Change-Id: I6fdea9cbb8c6041663bd36f68f1cae4b435c1f9b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1421 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-04Make the device tree available in the rom stageStefan Reinauer
We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1398 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-03Fix mainboard level enable_dev()Kyösti Mälkki
Commit 188e3c2ff06a82f61d7d71e610b32b1a250c0a45 dropped mainboard out of the static device tree. This left dev_root->chip_ops unset, and mainboard_ops.enable_dev() was no longer called. Change-Id: I6d447c8049a66041b8bb36ec9aac3e7e0d20a99b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1374 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-08-02AMD and GFXUMA: move setup_uma_memory() to northbridgeKyösti Mälkki
UMA region can be determined at any time after the amount of RAM is known and before the uma_resource() call. Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1379 Reviewed-by: Zheng Bao <zheng.bao@amd.com> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-01Intel Sandybridge: add reserved memory as resourcesKyösti Mälkki
Reserved memory resources will get removed from memory table at the end of write_coreboot_table(), Change-Id: I02711b4be4f25054bd3361295d8d4dc996b2eb3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1372 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
This reverts commit 042c1461fb777e583e5de48edf9326e47ee5595f. It turned out that sending IPIs via broadcast doesn't work on Sandybridge. We tried to come up with a solution, but didn't found any so far. So revert the code for now until we have a working solution. Change-Id: I7dd1cba5a4c1e4b0af366b20e8263b1f6f4b9714 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1381 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-27Allocators for different memory regions typesKyösti Mälkki
Hide some details of the resource allocator from rest of the world. These should come in handy when fixing some aspects of MTRR setup. Change-Id: I8acad98f25e56cd8bae64fb52539d81ce94f9c73 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1367 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-24Add support for HM70 and NM70 LPC bridgeStefan Reinauer
This lets the SPI driver and the LPC driver know about HM70 and NM70. Change-Id: Id2f1e0e5586a2f7200b2d24785df3f2be890da98 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1300 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-20Allow shutting down internal graphics if plugin graphics are preferredPatrick Georgi
VGA is this part-legacy thing that can cause trouble... For this, introduce device_t->disable(dev) method, in which a driver can take care to deregister the device if necessary. Change-Id: I3fecec07f402e530458b79eda30b2c274101fefa Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1251 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-16Change uma_resource() to use new type IORESOURCE_UMA_FB.Kyösti Mälkki
MTRR setup code can detect this and mark it as UC/WT/WC as suitable for the specific hardware. Change-Id: Ib7a3d450fc7c19e3ca72767dfb350412dd35c971 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1214 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Define global uma_memory variablesKyösti Mälkki
Use of the uma_memory_base and _size variables is very scattered. Implementation of setup_uma_memory() will appear in each northbridge. It should be possible to do this setup entirely in northbridge code and get rid of the globals in a follow-up. Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Add global uma_resource()Kyösti Mälkki
Like ram_resource(), but reserved and not cacheable. Switch all AMD northbridges to use this one. Change-Id: I88515c6a0f59f80fd8607c390d0d4a2a35d805f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1203 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13MPTAPLE: generate from devicetree.cbSven Schnelle
This patch adds support for autogenerating the MPTABLE from devicetree.cb. This is done by a write_smp_table() declared weak in mpspec.c. If the mainboard doesn't provide it's own function, this generic implementation is called. Syntax in devicetree.cb: ioapic_irq <APICID> <INTA|INTB|INTC|INTD> <INTPIN> The ioapic_irq directive can be used in pci and pci_domain devices. If there's no directive, the autogen code traverses the tree back to the pci_domain and stops at the first device which such a directive, and use that information to generate the entry according to PCI IRQ routing rules. Change-Id: I4df5b198e8430f939d477c14c798414e398a2027 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1138 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12Lenovo X60: correct SDHCI write protect polarityJonathan A. Kollasch
Change-Id: I916deffe2c692042f7e54c936902e77770ee69df Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/1205 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-05PCI Type2 config must dieRonald G. Minnich
PCI Type 2 config was a strange and never-used config mechanism. It is unlikely that in the 13 years of coreboot's existence that type 2 was ever used; it just made life complicated for everyone. It lived long enough in coreboot to be replaced by mmioconf. Prior to making the device tree visible in romstage we want to get rid of type2. Delete two files we don't need any more (yay!). Replace two functions with one: pci_config_default, which returns a pointer to the default config method. At some future time this may change to mmio but for now it is old type1 style. Change-Id: Icc4ccf379a89bfca8be43f305b68ab45d88bf0ab Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1159 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-03AGESA F15 wrapper for Trinityzbao
The wrapper for Trinity. Support S3. Parme is a example board. Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1156 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
The current code for initializing AP cpus has several shortcomings: - it assumes APIC IDs are sequential - it uses only the BSP for determining the AP count, which is bad if there's more than one physical CPU, and CPUs are of different type Note that the new code call cpu->ops->init() in parallel, and therefore some CPU code needs to be changed to address that. One example are old Intel HT enabled CPUs which can't do microcode update in parallel. Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1139 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-30Add support for Panther Point to SPI driverStefan Reinauer
Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1048 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-10Add SPI flash driverStefan Reinauer
This driver is taken from u-boot and adapted to match coreboot. It still contains some hacks and is ICH specific at places. Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/997 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01Allow device ID arrays in the PCI driver structureVadim Bendebury
Many PCI devices share the very same driver despite having different PCI device IDs, which causes a lot of copy and paste of driver definitions. This change introduces a way to specify the array of acceptable device IDs in a single driver entry. As an example the Intel {Sandy|Ivy} Bridge SATA driver is being modified to use a single driver structure for all different SATA controller flavors, a few more Ivy Bridge IDs are being added as well. BUG=none TEST=manual . modified coreboot brought up an Ivy Bridge platform all the way to Linux login screen. Change-Id: I761c5611b93ef946053783f7a755e6c456dd6991 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/982 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-02Add a helper function to determine the number of enabled CPUsStefan Reinauer
Change-Id: Ia72926002571e0f250849fa5db048bd8b2e92400 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/821 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29Add support for enabling PCIe Common Clock and ASPMDuncan Laurie
These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/735 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-27Add RDC R8610 PCI IDs.Rudolf Marek
Change-Id: I3f3585f15265aa1377f72ba23accf1adb08cb8ac Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/806 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-09Add helper function to find a Local APIC by ID in the device tree.Duncan Laurie
Change-Id: Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/695 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-02-16pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci idsKerry Sheh
Change-Id: I13905f5730d08510c8f0f6e652f41a679d618d1b Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/609 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-07Add OPROM mapping support to corebootStefan Reinauer
This allows to add a PCI ID mapping function for option roms so that the same option rom can be used for a series of devices / PCI IDs. Intel and AMD often use the same option rom for a number of PCI devices with differend IDs. A function to implement such a mapping could look like this (or anything else appropriate): /* some vga option roms are used for several chipsets but they only have one * PCI ID in their header. If we encounter such an option rom, we need to do * the mapping ourselfes */ u32 map_oprom_vendev(u32 vendev) { u32 new_vendev=vendev; switch(vendev) { case 0xa0118086: new_vendev=0xa0018086; break; } return new_vendev; } Change-Id: I1be7fe113b895075d43ea48fe706b039cef136d2 Reviewed-on: http://review.coreboot.org/573 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-01-24RD890: pci_ids updateKerry Sheh
RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets, add their pci device id respectively. Change-Id: I30c62c5802279ff2ee8da1cae41395e6899339bb Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/558 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-12SB800: Sata Enable bus master and enable ahci for AHCI/RAID modeKerry Sheh
In order to make sure AHCI/RAID ROM works correctly For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should enable bus master and the ahci also should be enabled. Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200 Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/248 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-03pci_ids: Add sb800 SATA device raid mode device idKerry Sheh
sb800 SATA device have different device id with different configure mode, 4392h for RAID mode, 4393h for RAID5 mode Change-Id: If54f7751f531c94ee725309a2a5c255390935ead Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/226 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-26Add automatic SMBIOS table generationSven Schnelle
Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/152 Tested-by: build bot (Jenkins)
2011-06-28Addition of Family12/SB900 wrapper codeefdesign98
This change adds the wrapper code for the AMD Family12 cpus and the AMD Hudson-2 (SB900) southbridge to the cpu, northbridge and southbridge folders respectively. Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/53 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-03Correct wrong PCI ID for VIA K8M890 Chrome.Alexandru Gagniuc
With the K8T800/M800 patch from r6367 the PCI IDs for the VIA chrome were moved to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly. (3220 instead of 3230). This patch defines the correct PCI ID for this device. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15Enable AHCI mode and hide IDE controller to reduce boot time.Scott Duplichan
Note: enable AHCI in seabios and apply seabios patch: http://www.mail-archive.com/seabios@seabios.org/msg00437.html Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-09Adds RS740 HT and internal graphics PCI ids.Ivaylo Valkov
Signed-off-by: Ivaylo Valkov <ivaylo@e-valkov.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20pci1x2x: add PCI1510 device IDsSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-27Add AMD SR56x0 support.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 17:54:36 +0000