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This patch adds Lewisburg C62x Series PCH support by adding the
Production and Super SKUs of the following PCI devices:
- LPC or eSPI Controllers,
- PCI Express Root Ports,
- SSATA and SATA Controllers,
- SMBus,
- SPI Controller,
- ME/HECI,
- Audio,
- P2SB,
- Power Management Controller.
These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
(PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: I7eaf2c1bb725ffed66f86c023c415ad17fe5793d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
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Removes PCI_DEVICE_ID_INTEL_SKL_ID_DT because this PCI Id duplicates
PCI_DEVICE_ID_INTEL_SKL_ID_S_4 (0x191f)
Change-Id: I028a22d6a42c040f5991a03def3e410f515c1c7f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BUG=b:139798422
TEST=Build and boot CMLRVP.
Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
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Add cometlake EMMC controller ID
BUG=none
BRANCH=none
TEST=none
Change-Id: I3943dad57918df3df7885c2e2d3a86ab0e1d6008
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Allow a driver to return device specific _HID, which will be consumed by
acpigen in order to generate proper SSDTs.
Change-Id: Ibb79eb00c008a3c3cdc12ad2a48b88a055a9216f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35006
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This Device ID is specific to CML, since it is obtained by reading ISH
configuration RO register.
In order to export ISH to kernel PCI device tree, this number must be
included in list of devices supported.
Change-Id: I6d245f1b3f0d0cfec77c31033eb20f147fd3d870
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34687
Reviewed-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Many peripheral drivers across different SoCs regularly face the same
task of piping a transfer buffer into (or reading it out of) a 32-bit
FIFO register. Sometimes it's just one register, sometimes a whole array
of registers. Sometimes you actually transfer 4 bytes per register
read/write, sometimes only 2 (or even 1). Sometimes writes need to be
prefixed with one or two command bytes which makes the actual payload
buffer "misaligned" in relation to the FIFO and requires a bunch of
tricky bit packing logic to get right. Most of the times transfer
lengths are not guaranteed to be divisible by 4, which also requires a
bunch of logic to treat the potential unaligned end of the transfer
correctly.
We have a dozen different implementations of this same pattern across
coreboot. This patch introduces a new family of helper functions that
aims to solve all these use cases once and for all (*fingers crossed*).
Change-Id: Ia71f66c1cee530afa4c77c46a838b4de646ffcfb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Some files under src/ec are built for both ramstage
and SMM. This change provides declarations of the
required struct to have __SMM__ guards removed from
those files.
Change-Id: Ic0c01a11f29381153f19378d5bc4559db8126e00
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I92e2adb32d19ff49bdef353e1f191c4960ce0d18
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I7176efdd1000789a093a1b4e243b4b150e6bb06f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34864
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ability to decode basic fields of DDR4 SPDs and produce SMBIOS table
17. XMP, schemas, extended field parising is totally not yet implemented.
Also, put CRC function used in DDR2, DDR3 and DDR4 ina common file.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: If3befbc55cf37e1018baa432cb2f03743b929211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Caller needs to take into account that bus numbers may
have not been assigned yet. Same issue existed before
with early ramstage and mostly does not cause problems
when used with static devices on bus 0.
Change-Id: I4865b4277dbc858c8c2ffd2052defcaa1a92173c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34614
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ...
- adds the PCH ID for C232 chipset,
- renames "Premium" chipset to "HM170" (because of same IDs),
- reorders the Skylake-H PCH IDs ascending by hex values.
Used documents:
- Intel 332690-005EN
Change-Id: I859975fe7bcd3c10dead8fe150a2fbead9c64a51
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I7abca61db61d2f2df149ca601631c45d8c4f342e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34613
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* PCH IDs: H310, H370, Z390, B360, C242, HM370
* IGD IDs: Another variant of UHD-Graphics 630
* MCH/CPU IDs: Used at i3-8100
Used documents:
* 337347-005
TESTED=Gigabyte Z390M Gaming
Change-Id: I5be88ef23359c6429b18f17bcffbffb7f10ba028
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34600
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the ID for Picasso's D0F0.
Change-Id: Id83dfecd628a6ee67bf61e390569da6cfc455a7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Make the Trinity IOMMU ID naming consistent with other products.
Change-Id: Id5a03d44a2ca21061bb22f9e61b26e42d91f9d96
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Put the devices in Family/Model order instead of a mostly
chronological order.
Change-Id: I425736012b3bb68c9e0b417e90ff5261d1193aba
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Apply uniform style of error messages for missing device
nodes and chip_info.
Change-Id: I70def4599509b8193e44ea3f02c4906f865b4469
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Only needed in ramstage, and only for MP tables.
Change-Id: Ia7c1e153b948aeefa4c3bea4920b02a91a417096
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33922
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Add CPU, MCH & IGD IDs for new Coffeelake SKUs
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
- Make some minor alignments & naming corrections to align with the rest
TEST= build, boot to both Linux & windows OS on CFL H & S platforms
and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fix regression with commit
903b40a soc/intel: Replace uses of dev_find_slot()
Platforms where FSP hides PCI devices before enumeration
may halt with error message 'PCI: dev is NULL!'.
The workaround here is to print an error message revealing
the faulty source code function and revert to old behaviour
of dev_find_slot().
Change-Id: I5eab3e7f1993b686103eaa257aacda379dc259fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34285
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7a361187570716df94a3fd441ae78c0f805b1dda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33921
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These didn't align with the usual naming conventions and contained some
errors beside.
Change-Id: I45033d4cb998a85fc0bec00c54e207226f42de4e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ibf72a8db2e4292e5d5bb67b8778e1d1ebfa19632
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34164
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic57ccf48988afbbba256172a7540bb02b88d1bbd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34163
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It is recommended to never reference PCI busses
using a static number. There is exception with
OPROM execution, where we want to translate the
bus number captured from the actual IO operation
into a matching device node in the devicetree.
Change-Id: I733c645ac5581c000b4cd6cdc05829cd039324d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I48c0de73338430282ce1a4442bbeb7c867dc174c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This is used a lot, cache the result so search
of domain from devicetree is only done once.
Improvement only applies when MAYBE_STATIC evaluates
to static.
Change-Id: If675abb632fe68acd59ba0bdfef854da3e0839a9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Wrap the simple romstage implementation to be called
from ramstage.
Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31755
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4ac67d1577229e63424dd7fd0ff84d1acfe826c3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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- Add documentation comment
- Use 'unsigned int' to make checkpatch happy
- Return early if no more links need to be added
- Add error handling if malloc fails
- Clean up whitespace
Change-Id: I70976ee2539b058721d0ae3c15edf279253cd9b7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229634
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33238
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This function is duplicated in many AMD northbridge files, and all
the definitions have started to diverge somewhat. This moves a single
copy into device utils and deletes the rest. The function definition
from nb/amd/amdfam10 was chosen to be kept, since it contains several
fixes from commit 59d609217b (AMD fam10: Fix add_more_links) that
the others don't have.
For the ease of diffing, the checkpatch lints and other small cleanups
will be done in a follow-up patch.
Change-Id: I5ea73126092449db3f18e19ac0660439313072de
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33237
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI,
hence modify SoC code to reflect the same.
This patch replaces all SoC specific PCI LPC references with ESPI
except anything that touches intel common code block.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
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Add Skylake C236 to the PCH Table. The one which was already in there is
actually the CM236 and not the C236. This can be checked in datasheet:
100-series-chipset-datasheet-vol-1 p. 25.
Change-Id: I435927f15e9d3219886375426b09c68632dfe3d9
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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These are documented in the Intel Datasheet entitled
"6th Generation Intel® Processor Datasheet for S-Platforms"
"6th Generation Intel® Processor Datasheet for H-Platforms" (Volume 2)
Without them, coreboot fails to properly inform the payload of the
amount of available memory.
Signed-off-by: Keno Fischer <keno@juliacomputing.com>
Change-Id: I5b810c6415c4aa0404e5fa318d2c8db292566b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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SMBIOS Type41 Entries will be automatically created. Type 41 entries
define attributes of the onboard devices.
Change-Id: Idcb3532a5c05666d6613af4f303df85f4f1f6e97
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32910
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib11981543575311a32896df385d44cf30aa9387f
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32964
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I496b3a91f765d4fa137c32c9ee1e244803fc25d8
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32850
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments.
The field is valid for PCI devices and only compiled if SMBIOS table
generation is enabled.
smbios_slot_desc arguments:
1. slot type
2. slot lenth
3. slot designation (optional)
4. slot data width (optional)
Example:
device pci 1c.1 on
smbios_slot_desc "21" "3" "MINI-PCI-FULL" "8"
end # PCIe Port #2 Integrated Wireless LAN
Tested on Lenovo T520.
Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Added IDs for:
- H170
- Z170
- Q170
- Q150
- B150
Used documents:
- 332690-005EN
Tested on Gigabyte GA-Z170N-WIFI
Change-Id: If20a2b764afa02785a97948893dbc5b5f60aff60
Signed-off-by: Marius Genheimer <mail@f0wl.cc>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32517
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
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The effect of pointer aliasing on writes is that any data on CPU
registers that has been resolved from (non-const and non-volatile)
memory objects has to be discarded and resolved. In other words, the
compiler assumes that a pointer that does not have an absolute value
at build-time, and is of type 'void *' or 'char *', may write over
any memory object.
Using a unique datatype for MMIO writes makes the pointer to _not_
qualify for pointer aliasing with any other objects in memory. This
avoid constantly resolving the PCI MMCONF address, which is a derived
value from a 'struct device *'.
Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add HrP 9560 module device ID (0x06F0) into device/pci_ids.h file.
TEST=HrP module is getting detected during PCI enumeration on CMLRVP
Change-Id: I8f6d89b1c6d03e2497f6b345a520323f45247d7e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32096
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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This patch cleans up remaining uses of raw boolean Kconfig values I
could find by wrapping them with CONFIG(). The remaining naked config
value warnings in the code should all be false positives now (although
the process was semi-manual and involved some eyeballing so I may have
missed a few).
Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch adds generic log to perform subsystem programming
based on header type.
Type 0: subsystem offset 0x2C
Type 2: subsystem offset 0x40
Type 1: Read CAP ID 0xD to know cap offset start, offset 4 to locate
subsystem vendor id.
Change-Id: Id8aed6dac24517e93cd55d6bb3b254b7b4d950d3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This patch creates new resource function to perform allocation
of IO resource, similar to mmio_resource() function does for MMIO.
Change-Id: I3fdcabb14302537d6074bfd6a362690c06b66bb5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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In the current state of the tree we do not utilise the
mechanism of having per-device overrides for PCI bus
ops.
This change effectively inlines all PCI config accessors
for ramstage as well.
Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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