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path: root/src/include
AgeCommit message (Expand)Author
2012-04-16S3 code in coreboot public folder.zbao
2012-04-12Add support for aligned allocationRon Minnich
2012-04-06Fixes and Sandybridge support for lapic cpu initStefan Reinauer
2012-04-06Add constants for fast path resume copyingStefan Reinauer
2012-04-05Fill out ChromeOS specific coreboot table extensionsStefan Reinauer
2012-04-04Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
2012-04-03smbios: add support for onboard devices extended informationStefan Reinauer
2012-04-02Add a helper function to determine the number of enabled CPUsStefan Reinauer
2012-04-02Align: Make sure 1 is treated as unsigned long instead of intStefan Reinauer
2012-03-30Make MTRR min hole alignment 64MBDuncan Laurie
2012-03-30Add more timestamps in coreboot.Stefan Reinauer
2012-03-30Add timestamps for selfboot and acpi wakeDuncan Laurie
2012-03-30Add TPM support to corebootStefan Reinauer
2012-03-30Add an option to keep the ROM cached after romstageStefan Reinauer
2012-03-29Add infrastructure for global data in the CAR phase of bootGabe Black
2012-03-29Detect whether the OXPCIE card is really present while in the ROM stage.Gabe Black
2012-03-29Add support for enabling PCIe Common Clock and ASPMDuncan Laurie
2012-03-29Refactor publishing CBMEM addresses through coreboot table.Vadim Bendebury
2012-03-29Add timestamp table pointer to the coreboot table.Vadim Bendebury
2012-03-29CBMEM CONSOLE: Add CBMEM type for console buffer.Vadim Bendebury
2012-03-29CBMEM CONSOLE: Add CBMEM console driver implementation.Vadim Bendebury
2012-03-29Increase CBMEM to accommodate larger console.Vadim Bendebury
2012-03-28Add cmos helper functions for reading/writing a dwordDuncan Laurie
2012-03-28Add timestamp collecting to coreboot.Vadim Bendebury
2012-03-28Initialize CBMEM early.Vadim Bendebury
2012-03-27Add RDC R8610 PCI IDs.Rudolf Marek
2012-03-16xchg is atomic with side-effectsPatrick Georgi
2012-03-14Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is availableGabe Black
2012-03-09Increase size of the coreboot table areaStefan Reinauer
2012-03-09Add helper function to find a Local APIC by ID in the device tree.Duncan Laurie
2012-03-09move console includes to central console/console.hStefan Reinauer
2012-03-09Add an implementation for the memchr library functionGabe Black
2012-03-08Unify Local APIC address definitionsPatrick Georgi
2012-02-16pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci idsKerry Sheh
2012-02-16AGESA F15: AGESA family15 model 00-0fh cpu wrapperKerry Sheh
2012-02-13AMD Geode cpus: apply un-written naming rulesKyösti Mälkki
2012-02-07Add OPROM mapping support to corebootStefan Reinauer
2012-01-24RD890: pci_ids updateKerry Sheh
2012-01-23post code: Replaced hard-coded post code with macroVikram Narayanan
2012-01-12lib: add ram_check_nodieSven Schnelle
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
2011-12-13Fix CMOS handling for non-USE_OPTION_TABLE configurationPatrick Georgi
2011-11-01remove trailing whitespaceStefan Reinauer
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
2011-10-31Fix usb debug dongle supportSven Schnelle
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
2011-10-21Extend coreboot table entry for serial portsStefan Reinauer
2011-10-21Add macros for 64bit byte order swappingStefan Reinauer
2011-10-13Enable/fix compilation of i8254 code in ram stage.Stefan Reinauer