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2011-05-10Change read_option() to a macro that wraps some API uglynessPatrick Georgi
Simplify read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault) to read_option(foo, somedefault) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-09Adds RS740 HT and internal graphics PCI ids.Ivaylo Valkov
Signed-off-by: Ivaylo Valkov <ivaylo@e-valkov.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-26Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as anStefan Reinauer
example. This newer version reflects the recent changes to further simplify the console code and partly gets rid of some hacks in the previous version. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-22The UART divider should be calculated based on the base frequencyStefan Reinauer
and baudrate, not hardcoded in addition to that. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21more ifdef -> if fixesStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21some ifdef --> if fixesStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20Simplify coreboot's console/console.hStefan Reinauer
- shift most (romcc) code out of console.h into arch/x86/lib/romcc_console.c - rename arch/x86/lib/printk_init.c to .../romstage_console.c - drop FUNCTIONS_FOR_PRINT since __console_tx_* are already functions, so there should not be any side effects to eliminating another indirection. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20pci1x2x: add PCI1510 device IDsSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20drop dead uart init code.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11Unify use of post_codeAlexandru Gagniuc
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-10In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.Stefan Reinauer
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html It's about time we follow this advice. Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and drop unused CPP define Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-27Add AMD SR56x0 support.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01Fix a simple whitespace error in src/include/device/device.hSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> Reported-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01Add subsystemid option to sconfigSven Schnelle
Allow user to add 'subsystemid <vendor> <device> [inherit]' to devicetree.cb for PCI and PCI domain devices. Example: device pci 00.0 on subsystemid dead beef end If the user wants to have this ID inherited to all subdevices/functions, he can add 'inherit', like in the following example: device pci 00.0 on subsystemid dead beef inherit end If the user don't want to inherit a Subsystem for a single device, he can specify 'subsystemid 0 0' on this particular device. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-16Extended K8T890 driver to include the K8T800 and K8M800 northbridgesAlexandru Gagniuc
The K8T800 is almost identical to the K8T800Pro, also added to this patch. The K8T800_OLD is also defined, which is an older version of the K8T800, but which has no driver and early HT code yet. Also extended the K8M890 VGA driver to work for the K8M800 (not tested). According to the datasheet, the K8T890 and K8T800 are similar enough to be able to use the same initialization code. At least for the K8T800, this is sufficient to have a working HT link with the CPU, and to initialise the V-Link to the southbridge. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347.Frank Vibrans
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Marc Jones <marcj303@gmail.com git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-03Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functionsPatrick Georgi
This is so that boards can determine them on runtime based on hardware properties, if so desired. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Joseph Kellermann <Joseph.Kellermann@heitec.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-31Add PCI ID's for VIA K8T800 and K8M800 northbridges.Alexandru Gagniuc
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-28This patch gets usbdebug console working in romstage.Stefan Reinauer
- actually hook up usbdebug in printk/print_ for romstage - make usbdebug.c more similar to the Linux kernel version it was originally derived from. - increase retries and timing for usbdebug init (at least one chipset seems to need this) - src/pc80/usbdebug_serial.c is not needed - some small console cleanups Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19Revert r5902 to make code more readable again. At least three people like toStefan Reinauer
have this go away again. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Kevin O'Connor <kevin@koconnor.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19Now that the VIA code is run above 1Meg (like other boards), it shouldKevin O'Connor
cache that range instead of the first 1Meg. This reduces boot time by about 1 second on epia-cn. This patch also adds a MTRRphysMaskValid bit definition. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18Move option table (cmos.layout's binary representation)Patrick Georgi
to CBFS and adapt coreboot to use it. Comments by Stefan and Mathias taken into account (except for the build time failure if the table is missing when it should exist and the "memory leak" in build_opt_tbl) Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01Add AMD SB800 southbridge support via cimx_wrapper.Kerry She
Signed-off-by: Kerry She <Kerry.she@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-31Add RS785(RS880) support. Just few pci_ids.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29-Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)Nils Jacobs
to FG (FooGlue). As the GX2 has no VIP port. -Change the Memmory setup MSR register names so they correspond better to the databook. (Part1) This is less confusing for beginners. -Add a MSR printing function to northbridge.c like in the Geode LX code. -Remove the AES register names.(GX2 has no AES registers) -Delete some unused code. -Clean up GX2 northbridge code to match Geode LX code. -Add missing copyright header to northbridge.c. -Move hardcoded IRQ defining from northbridge.c to irq_tables.c . Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26Replace Geode GX2 MSR addresses for GLCP on GLIU1 with namesNils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26Clean up Geode GX2 comments, whitespace and coding style. Trivial.Nils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18SMM for AMD K8 Part 1/2Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17fix the tree again. Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17drop one more version of doing serial uart output differently.Stefan Reinauer
coreboot made it kind of complicated to print a character on serial. Not quite as complicated as UEFI, but too much for a good design. Fix it. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17guard against the case that CONFIG_WAIT_BEFORE_CPUS_INIT is not defined at all.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13Compile cbmem.c instead of including it in romstage,Rudolf Marek
and do that only if resume is done. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13We hardcode highmemory size in every northbridge! This is bad, and ↵Rudolf Marek
especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic. Abuild tested. Please check all changes if I did not make any wrong while converting this to bytes. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11Following patch makes just one fadt.c file. For SB700.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11factor out cpu power management base into a separate file. And fix a bug inStefan Reinauer
model_1067x Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11After this has been brought up many times before, rename src/arch/i386 toStefan Reinauer
src/arch/x86. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08second round name simplification. drop the <component>_ prefix.stepan
the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the <componentname>_ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-05W83627DHG/W83627EHG fixups for virtual LDNs.Uwe Hermann
W83627DHG: - Add proper "virtual LDN" handling for the LDNs that need it (i.e., those that don't have their "enable" bit in bit 0 of the 0x30 register). - Fix various I/O masks in the pnp_dev_info[] array as per datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN. W83627EHG: - Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was mostly implemented already, though). - Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN. Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt for the virtual LDNs. include/device/pnp.h: Add comment that 'function' (which refers to the LDN and should probably be renamed later) has to be at least 16 bits wide. In theory LDNs could use u8, but due to the virtual LDN info being encoded in the "high byte" of 'function' it must be at least u16. asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV. ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial port 1 in this case) to avoid confusion. The global registers manipulated there are accessible from any LDN. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-221) wraps the s3 parts of chipset code/memory init code with if ↵Rudolf Marek
CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c 2) the patch implements get_cbmem_toc in chipset specific way if defined. On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached) 3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself. 4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right. I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again. Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22Printing coreboot debug messages on VGA console is pretty much useless, sinceStefan Reinauer
initializing VGA happens pretty much as the last thing before starting the payload. Hence, drop VGA console support, as we did in coreboot v3. - Drop VGA and BTEXT console support. Console is meant to be debugging only, and by the time graphics comes up 99% of the risky stuff has already happened. Note: This patch does not remove hardware init but only the actual output functionality. The ragexl driver needs some extra love, but that's for another day - factor out die() and post() - drop some leftover RAMBASE < 0x100000 checks. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: QingPei Wang<wangqingpei@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Some more DIMM0 related cleanups and deduplication.Uwe Hermann
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do. - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of romstage.c files and lots of spd_addr.h files. Don't even bother for those spd_addr.h which aren't even actually used, drop them right away. - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1, and 0xa0 with (DIMM0 << 1) where appropriate. - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0, SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC. - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines. - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do. Then, replace 0xa0 (which now becomes 0x50) with DIMM0. - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes. - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Unify DIMM SPD addressing. For Geode, change thePatrick Georgi
addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18For completeness sake: License header.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17Move Intel power management related defines to some central location.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-13MTRR related improvements for AMD family 10h and family 0Fh systemsScott Duplichan
-- When building for UMA, reduce the limit for DRAM below 4GB from E0000000 to C0000000. This is needed to accomodate the UMA frame buffer. -- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En and Tom2ForceMemTypeWB) are not set consistently across cores. -- Enable TOM2 only if DRAM is present above 4GB. -- Use AMD Tom2ForceMemTypeWB feature to avoid the need for variable MTRR ranges above 4GB. -- Add above4gb flag argument to function x86_setup_var_mtrrs. Clearing this flag causes x86_setup_var_mtrrs() to omit MTRR ranges for DRAM above 4GB. AMD systems use this option to conserve MTRRs. -- Northbridge.c change to deduct UMA memory from DRAM size reported by ram_resource. This corrects a problem where mtrr.c generates an unexpected variable MTRR range. -- Correct problem causing build failure when CONFIG_GFXUMA=1 and CONFIG_VAR_MTRR_HOLE=0. -- Reserve the UMA DRAM range for AMD K8 as is already done for AMD family 10h. Tested with mahogany on ECS A780G-GM with 2GB and 4GB. Tested with mahogany_fam10 on ECS A780G-GM with 2GB and 4GB. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-11Add pci id and ops for VT8237A SATA controllerTobias Diedrich
Needed to change class from raid to ide so seabios can boot from it. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07This adds the VT8237A LPC device id and the pci_driver struct inTobias Diedrich
vt8237r_lpc.c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-04Various cosmetic and coding style fixes in src/devices.Uwe Hermann
Also: - Improve a few code comments, fix typos, etc. - Change a few more variable types to u8/u16/u32 etc. - Make some very long lines fit into 80chars/line. - Drop a huge duplicated comment, use "@see" to refer to the other one. - Reduce nesting level a bit by restructuring some code chunks. - s/Config.lb/devicetree.cb/ in a few places. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-02This adds pci device ids and pci_driver structs for the K8T890 CFTobias Diedrich
variant. It also adds additional dev_find_device calls in k8t890_ctrl.c for subfunctions 3 and 7. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01Change Geode GX2 to use the auto DRAM detect code from Geode LX.Nils Jacobs
Also, change the GX2 boards to use it. Add a processor speed setting function in human readable MHz and remove the useless and broken PLLMSR settings (the processor speed was hardcoded to 366MHz in pll_reset.c). Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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