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2016-12-01lib: put romstage_handoff implementation in own compilation unitAaron Durbin
Instead of putting all the functions inline just put the current implementation into a C file. That way all the implementation innards are not exposed. Lastly, fix up the fallout of compilation units not including the headers they actually use. Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17648 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01romstage_handoff: add helper to determine resume statusAaron Durbin
Instead of having callers query the romstage handoff resume status by inspecting the object themselves add romstage_handoff_is_resume() so that the same information can be queried easily. Change-Id: I40f3769b7646bf296ee4bc323a9ab1d5e5691e21 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17647 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01romstage_handoff: remove code duplicationAaron Durbin
The same pattern was being used throughout the code base for initializing the romstage handoff structure. Provide a helper function to initialize the structure with the S3 resume state then utilize it at all the existing call sites. Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17646 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-30lib: Add library to handle SPD data in CBFS or DIMMNaresh G Solanki
Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-30soc/intel/common: Add save/restore for variable MRC dataAndrey Petrov
Piggy-back on existing MRC cache infrastructure to store variable MRC data. Only one set of data can be valid at given point of time. Currently this magically happens because region alignment is forced to 0x1000 and region itself is of the same size. This needs to be somehow programmatically enforced. Change-Id: I8a660d356ca760b8ff9907396fb9b34cb16cf1db Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-24x86 BIST: Fix missing includeKyösti Mälkki
Change-Id: I3d1a456f17073c99c9502da26e09cfde65380746 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17586 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24x86 BIST: Declare function with inline in header fileKyösti Mälkki
Change-Id: Ieb5f1668a715ceadd5fe5ba0d121c865f1886038 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17572 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-23AGESA binaryPI: Fix PCI ID namespaceKyösti Mälkki
The defines of device IDs reflects the vendor namespace the ID has been allocated from. Change-Id: Id98f45d5984752a9e8c0484d4cb94e93e55b12f6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17510 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-23include/device/early_smbus.h: Declare smbus write functionNaresh G Solanki
Add declaration for smbus write. Early smbus access also needs smbus write function specially to read spd for DDR4 wherein page has to be switched by smbus write. Change-Id: I246cbdf0b52923f01dd036f63df17bf9af043c9f Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22spi: Get rid of flash_programmer_probe in spi_slave structureFurquan Shaikh
flash_programmer_probe is a property of the spi flash driver and does not belong in the spi_slave structure. Thus, make spi_flash_programmer_probe a callback from the spi_flash_probe function. Logic still remains the same as before (order matters): 1. Try spi_flash_programmer_probe without force option 2. Try generic flash probing 3. Try spi_flash_programmer_probe with force option If none of the above steps work, fail probing. Flash controller is expected to honor force option to decide whether to perform specialized probing or to defer to generic probing. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I4163593eea034fa044ec2216e56d0ea3fbc86c7d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22spi: Get rid of max_transfer_size parameter in spi_slave structureFurquan Shaikh
max_transfer_size is a property of the SPI controller and not of the spi slave. Also, this is used only on one SoC currently. There is no need to handle this at the spi flash layer. This change moves the handling of max_transfer_size to SoC SPI driver and gets rid of the max_transfer_size parameter. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: I19a1d0a83395a58c2bc1614b24518a3220945a60 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17463 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-20device/dram/ddr3: Calculate CRC16 of SPD unique identifierKyösti Mälkki
Specification allows for the unique identifier bytes 117..125 to be excluded of CRC calculation. For such SPD, the CRC would not identify replacement between two identical DIMM parts, while memory training needs to be redone. Change-Id: I8e830018b15c344d9f72f921ab84893f633f7654 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17486 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-17rtc: Check update-in-progress bitMarshall Dawson
While the real-time clock updates its count, values may not be correctly read or written. On reads, ensure the UIP bit is clear which guarantees a minimum of 244 microseconds exists before the update begins. Writes already avoid the problem by disabling the RTC count via the SET bit. Change-Id: I39e34493113015d32582f1c280fafa9e97f43a40 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17369 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-16include/device/pci_ids.h: Correct Entertainment sub-classElyes HAOUAS
According to PCI LOCAL BUS SPECIFICATION, REV. 3.0 page 305, the sub-class for Entertainment en/decryption is 0x1010 Change-Id: Ia069e2ec328a8180fc1e2e70146c3710e703ee59 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17436 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-16vboot: TPM2 - report attempts to re-create NVRAM spacesVadim Bendebury
Currently the tlcl_define_space() function returns the same error value for any non-zero TPM response code. The thing is that the caller might want to allow attempts to re-create existing NVRAM spaces. This patch adds a new API return value to indicate this condition and uses it as appropriate. BRANCH=none BUG=chrome-os-partner:59654 TEST=for test purposes modified the code not to create the firmware space, wiped out the TPM NVRAM and booted the device. Observed it create kernel and MRC index spaces on the first boot and then reporting return code 0x14c for already existing spaces on the following restarts. Change-Id: Ic183eb45e73edfbccf11cc19fd2f64f64274bfb2 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/17422 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14vboot: Add new function for logging recovery mode switchesFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully Change-Id: I87cd675ea45a8b05a178cf64119bf5f9d8d218ca Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17408 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14elog: Update event log IDs for EC eventsFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully Change-Id: Idf2d377bf4709ea25616adfbde55f39798c0cd39 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17393 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-12drivers/intel/fsp2_0: track end of firmware notificationsAaron Durbin
The end of firmware notification is currently not being tracked so it's hard to get good data on how long it takes. Update the code to provide timestamp data as well as post codes. BUG=chrome-os-partner:56656 Change-Id: I74c1043f2e72d9d85b23a99b8253ac465f62a7f2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17373 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-11-12cpu/x86/mtrr: allow temporary MTRR range during corebootAaron Durbin
Certain platforms have a poorly performing SPI prefetcher so even if accessing MMIO BIOS once the fetch time can be impacted. Payload loading is one example where it can be impacted. Therefore, add the ability for a platform to reconfigure the currently running CPU's variable MTRR settings for the duration of coreboot's execution. The function mtrr_use_temp_range() is added which uses the previous MTRR solution as a basis along with a new range and type to use. A new solution is calculated with the updated settings and the original solution is put back prior to exiting coreboot into the OS or payload. Using this patch on apollolake reduced depthcharge payload loading by 75 ms. BUG=chrome-os-partner:56656,chrome-os-partner:59682 Change-Id: If87ee6f88e0ab0a463eafa35f89a5f7a7ad0fb85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17371 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11src/vboot: mark factory_initialze_tpm() as staticVadim Bendebury
This function is not used anywhere else in the code. BRANCH=none BUG=none TEST=reef and kevin boards (using tpm1.2 and tpm2.0 respectively) build successfully. Change-Id: Ifcc345ae9c22b25fdcfc2e547e70766021d27e32 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/17387 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-11intel post-car: Separate files for setup_stack_and_mtrrs()Kyösti Mälkki
Have a common romstage.c file to prepare CAR stack guards. MTRR setup around cbmem_top() is somewhat northbridge specific, place stubs under northbridge for platrform that will move to RELOCATABLE_RAMSTAGE. Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15762 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10vboot: Add support for recovery hash space in TPMFurquan Shaikh
1. Add a new index for recovery hash space in TPM - 0x100b 2. Add helper functions to read/write/lock recovery hash space in TPM 3. Add Kconfig option that can be selected by mainboards that want to define this space. 4. Lock this new space while jumping from RO to RW. BUG=chrome-os-partner:59355 BRANCH=None TEST=Verified use of recovery hash space on reef. Change-Id: I1cacd54f0a896d0f2af32d4b7c9ae581a918f9bb Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17273 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10antirollback: Sync TPM space indices with vboot libraryFurquan Shaikh
BUG=chrome-os-partner:59355 BRANCH=None TEST=Compiles successfully for reef. Change-Id: I27f2e10556214598d479e4a84e8949465e7da7d6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10mrc: Add support for separate training cache in recovery modeFurquan Shaikh
1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or RECOVERY_MRC_CACHE based on the boot mode. - If normal mode boot, use RW_MRC_CACHE, if available. - If recovery mode boot: - Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is requested explicity with retrain memory request. - Use RECOVERY_MRC_CACHE otherwise. 2. Protect RW and RECOVERY mrc caches in recovery and non-recovery boot modes. Check if both are present under one unified region and protect that region as a whole. Else try protecting individual regions. 3. Update training data in appropriate cache: - Use RW_MRC_CACHE if normal mode. - Use RECOVERY_MRC_CACHE if present in recovery mode. Else use RW_MRC_CACHE. 4. Add proper debug logs to indicate which training data cache is used at any point. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that correct cache is used in both normal and recovery mode on reef. Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17242 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10vboot: Add support for recovery mode with forced memory retrainingFurquan Shaikh
1. Add new function vboot_recovery_mode_memory_retrain that indicates if recovery mode requires memory retraining to be performed. 2. Add helper function get_recovery_mode_retrain_switch to read memory retrain switch. This is provided as weak function which should be implemented by mainboard just like {get,clear}_recovery_mode_switch. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified behavior of recovery mode with forced memory retraining on reef Change-Id: I46c10fbf25bc100d9f562c36da3ac646c9dae7d1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17241 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09cpu/intel: Add MSR to support enabling turbo frequencyShaunak Saha
This patch adds definition FREQ_LIMIT_RATIO MSR. FREQ_LIMIT_RATIO register allows to determine the ratio limits to be used to limit frequency. BUG=chrome-os-partner:58158 BRANCH=None Change-Id: I50a792accbaab1bff313fd00574814d7dbba1f6b Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/17211 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09ACPI S3: Remove HIGH_MEMORY_SAVE where possibleKyösti Mälkki
Add implementation to use actual requirements of ramstage size for S3 resume backup in CBMEM. The backup covers complete pages of 4 KiB. Only the required amount of low memory is backed up when ACPI_TINY_LOWMEM_BACKUP is selected for the platform. Enable this option for AGESA and binaryPI, other platforms (without RELOCATABLE_RAMSTAGE) currently keep their romstage ramstack in low memory for s3 resume path. Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15255 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-11-09string.h: only guard snprintf() with __ROMCC__Aaron Durbin
There's no need to keep the snprintf() declaration hidden for early stages. romcc is the entity that has issues. Therefore, be explicit about when to guard snprintf(). BUG=chromium:663243 Change-Id: Ib4d0879e52c3f73c6ca61ab75f672f0003fca71f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17289 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-07pci_ids.h: Correct recent AMD ID namesMarshall Dawson
Adjust the names to match AMD's convention for family and model. This patch is relevant for: Trinity & Richland: Family 15h Models 00h-0Fh Carrizo: Family 15h Models 60h-6Fh Mullins & Steppe Eagle: Family 16h Models 30h-3Fh Change-Id: I613b84ed438fb70269d789c9901f1928b5500757 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17169 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Martin Roth <martinroth@google.com>
2016-11-06soc/intel/common: log event when MRC cache is updatedAaron Durbin
Log when the MRC cache is attempted to be updated with status of success or failure. Just one slot is supported currently which is deemed 'normal'. This is because there are more slots anticipated in the future. BUG=chrome-os-partner:59395 Change-Id: I0f81458325697aff9924cc359a4173e0d35da5da Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17231 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-06elog: add sources to reflect full event type namespace usageAaron Durbin
Some events were added in other places, but coreboot's elog namespace wasn't updated. As such there's a collision with the thermtrip event. This change at least updates the elog information to reflect potential event type uage. BUG=chrome-os-partner:59395 Change-Id: Ib82e2b65ef7d34e260b7d7450174aee7537b69f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17230 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-06elog: fix default elog_add_event_raw() declarationAaron Durbin
When CONFIG_ELOG isn't used default empty inline functions are provided, however the elog_add_event_raw() had the wrong type signature. Fix that. BUG=chrome-os-partner:59395 Change-Id: Iaee68440bbafc1e91c88a7b03e283fc3e72de0a3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17232 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-06Add option to use Ada code in ramstageNico Huber
If selected, libgnat will be linked into ramstage. And, to support Ada package intializations, we have to call ramstage_adainit(). Change-Id: I11417db21f16bf3007739a097d63fd592344bce3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16944 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-02pci_ids.h: Add ID for amd/00670F00 northbridgeMarshall Dawson
Add the D18F0 device ID for the Stoney APU. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit c0fd7f70527c273bcbdce5655a21ca4de4854428) Change-Id: Ib599fc6119a3cef53f4f179c2fcd0e45905d81a4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17141 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02soc/intel/apollolake: Disable Monitor and Mwait featureVenkateswarlu Vinjamuri
Monitor/Mwait is broken on APL. So, it needs to be disabled. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: I12cd4280de62e0a639b43538171660ee4c0a0265 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/17200 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-31lib/prog_loaders: use common ramstage_cache_invalid()Aaron Durbin
All current implementations of ramstage_cache_invalid() were just resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE Kconfig option. Move that behavior to a single implementation within prog_loaders.c which removes duplication. Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17184 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-24RISCV: Clean up the common architectural codeRonald G. Minnich
This version of coreboot successfully starts a Harvey (Plan 9) kernel as a payload, entering main() with no supporting assembly code for startup. The Harvey port is not complete so it just panics but ... it gets started. We provide a standard payload function that takes a pointer argument and makes the jump from machine to supervisor mode; the days of kernels running in machine mode are over. We do some small tweaks to the virtual memory code. We temporarily disable two functions that won't work on some targets as register numbers changed between 1.7 and 1.9. Once lowrisc catches up we'll reenable them. We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual memory setup code. We now use the _stack and _estack from memlayout so we know where things are. As time goes on maybe we can kill all the magic numbers. Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17058 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-13vboot: Stop creating backup space in TPMDaisuke Nojiri
There is no code which uses the backup space in TPM created for vboot nvram. All chromebooks currently supported at the trunk store vboot nvram in flash directly or as a backup. BUG=chrome-os-partner:47915 BRANCH=none TEST=emerge-samus coreboot Change-Id: I9445dfd822826d668b3bfed8ca50dc9386f2b2b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5cee2d54c96ad7952af2a2c1f773ba09c5248f41 Original-Change-Id: Ied0cec0ed489df3b39f6b9afd3941f804557944f Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/395507 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://review.coreboot.org/16997 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06arm64: Use 'payload' format for ATF instead of 'stage'Simon Glass
Switch the BL31 (ARM Trusted Firmware) format to payload so that it can have multiple independent segments. This also requires disabling the region check since SRAM is currently faulted by that check. This has been tested with Rockchip's pending change: https://chromium-review.googlesource.com/#/c/368592/3 with the patch mentioned on the bug at #13. BUG=chrome-os-partner:56314 BRANCH=none TEST=boot on gru and see that BL31 loads and runs. Im not sure if it is correct though: CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1b440 size 15a75 Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x18104800 memsize 0x117fbe0 srcaddr 0x100038 filesize 0x15a3d Loading segment from ROM address 0x000000000010001c Entry Point 0x0000000018104800 Loading Segment: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d using LZMA [ 0x18104800, 18137d90, 0x192843e0) <- 00100038 Clearing Segment: addr: 0x0000000018137d90 memsz: 0x000000000114c650 dest 0000000018104800, end 00000000192843e0, bouncebuffer ffffffffffffffff Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 125150 exit 1 Jumping to boot code at 0000000018104800(00000000f7eda000) CPU0: stack: 00000000ff8ec000 - 00000000ff8f0000, lowest used address 00000000ff8ef3d0, stack used: 3120 bytes CBFS: 'VBOOT' located CBFS at [402000:44cc00) CBFS: Locating 'fallback/bl31' CBFS: Found @ offset 10ec0 size 8d0c Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x10000 memsize 0x40000 srcaddr 0x100054 filesize 0x8192 Loading segment from ROM address 0x000000000010001c code (compression=1) New segment dstaddr 0xff8d4000 memsize 0x1f50 srcaddr 0x1081e6 filesize 0xb26 Loading segment from ROM address 0x0000000000100038 Entry Point 0x0000000000010000 Loading Segment: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192 lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192 using LZMA [ 0x00010000, 00035708, 0x00050000) <- 00100054 Clearing Segment: addr: 0x0000000000035708 memsz: 0x000000000001a8f8 dest 0000000000010000, end 0000000000050000, bouncebuffer ffffffffffffffff Loading Segment: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26 lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26 using LZMA [ 0xff8d4000, ff8d5f50, 0xff8d5f50) <- 001081e6 dest 00000000ff8d4000, end 00000000ff8d5f50, bouncebuffer ffffffffffffffff Loaded segments INFO: plat_rockchip_pmusram_prepare pmu: code d2bfe625,d2bfe625,80 INFO: plat_rockchip_pmusram_prepare pmu: code 0xff8d4000,0x50000,3364 INFO: plat_rockchip_pmusram_prepare: data 0xff8d4d28,0xff8d4d24,4648 NOTICE: BL31: v1.2(debug): NOTICE: BL31: Built : Sun Sep 4 22:36:16 UTC 2016 INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 INFO: plat_rockchip_pmu_init(1189): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x18104800 INFO: SPSR = 0x8 Change-Id: Ie2484d122a603f1c7b7082a1de3f240aa6e6d540 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8c1d75bff6e810a39776048ad9049ec0a9c5d94e Original-Change-Id: I2d60e5762f8377e43835558f76a3928156acb26c Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376849 Original-Commit-Ready: Simon Glass <sjg@google.com> Original-Tested-by: Simon Glass <sjg@google.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16706 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01cpu/amd/model_fxx: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside cpu/amd/model_fxx. Change-Id: Iac7571956ed2fb927a6b8cc88514e533f40490d0 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16437 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-20src/include: Add space around operatorsElyes HAOUAS
Change-Id: I0ee4c443b6861018f05cfc32135d632fd4996029 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16614 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-19arch/x86,lib: make cbmem console work in postcar stageAaron Durbin
Implement postcar stage cbmem console support. The postcar stage is more like ramstage in that RAM is already up. Therefore, in order to make the cbmem console reinit flow work one needs the cbmem init hook infrastructure in place and the cbmem recovery called. This call is added to x86/postcar.c to achieve that. Additionally, one needs to provide postcar stage cbmem init hook callbacks for the cbmem console library to use. A few other places need to become postcar stage aware so that the code paths are taken. Lastly, since postcar is backed by ram indicate that to the cbmem backing store. BUG=chrome-os-partner:57513 Change-Id: I51db65d8502c456b08f291fd1b59f6ea72059dfd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16619 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-19console: honor CONFIG_POSTCAR_CONSOLEAaron Durbin
The declarations for console_init() were unconditionally exposed even though there is a Kconfig option. Correct this by honoring the CONFIG_POSTCAR_CONSOLE condition. BUG=chrome-os-partner:57513 Change-Id: Id45ae3d7c05a9f4ebcf85c446fc68a709513bb0f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16617 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-12arch/arm: Add armv7-r configurationHakim Giydan
This change adds armv7-r support for all stages. armv7-r is an ARM processor based on the Cortex-R series. Currently, there is support for armv7-a and armv7-m and armv7-a files has been modfied to accommodate armv7-r by adding ENV_ARMV7_A, ENV_ARMV7_R and ENV_ARMV7_M constants to src/include/rules.h. armv7-r exceptions support will added in a later time. Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15335 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12cpu/x86: Move fls() and fms() to mtrr.hRizwan Qureshi
Move the funtion to find most significant bit set(fms) and function to find least significant bit set(fls) to a common place. And remove the duplicates. Change-Id: Ia821038b622d93e7f719c18e5ee3e8112de66a53 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16525 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-08edid: Fix a function signatureNico Huber
Change-Id: Id69cecb5cdd21c2d92aca74658f39c790f7b7b01 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/15211 Tested-by: build bot (Jenkins)
2016-09-05src/include: Improve code formattingElyes HAOUAS
Change-Id: Ic8ffd26e61c0c3f27872699bb6aa9c39204155b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16390 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-04device/pci.h: change #ifdef argument to __SIMPLE_DEVICE__Antonello Dettori
Change the argument to #ifdef from __PRE_RAM__ to __SIMPLE_DEVICE__ in order to account for the coreboot stages that do not define device_t and are not __PRE_RAM__ (i.e. smm) device_t Change-Id: Ic6e9b504803622b60b5217c9432ce57caefc5065 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16369 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-28src/include: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I307d37cdf2647467d4c88dfa4be5c66c8587202e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16285 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-03 22:10:23 +0000