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2020-08-24soc/amd/picasso: Add console & timestamp buffers to psp_verstageMartin Roth
Create areas for console & timestamp data in psp_verstage and pass it to the x86 to save for use later. BUG=b:159220781 TEST=Build & Boot trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I41c8d7a1565e761187e941d7d6021805a9744d06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-21lib: Update fmap cache error for psp_verstageMartin Roth
The assumption was that the fmap cache would be initialized in bootblock, otherwise an error is shown. This error is showing up in psp_verstage when the fmap cache is initialized there, so create a new ENV value for ENV_INITIAL_STAGE. BUG=None TEST=Boot, see that error message is gone from psp_verstage Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I142f2092ade7b4327780d423d121728bfbdab247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43488 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21acpi: add more AML generation functionsAaron Durbin
Add the following functions to acpi AML generation code: acpigen_write_to_integer_from_namestring() acpigen_write_create_byte_field() acpigen_write_create_word_field() acpigen_write_create_dword_field() acpigen_write_create_qword_field() BUG=b:163583825 Change-Id: Ida151aff68f90012b16df2383fb96ddb87c3fb9c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44641 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21include/asan.h: Add missing includesElyes HAOUAS
<stdint.h> and <stddef.h> are missing. Change-Id: I10520013bb5ceb3aec0d24715f371f77e4300a70 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2020-08-21arch/x86: Add support for ASan to memory functionsHarshit Sharma
Compiler's instrumentation cannot insert asan memory checks in case of memory functions like memset, memcpy and memmove as they are written in assembly. So, we need to manually check the memory state before performing each of these operations to ensure that ASan is triggered in case of bad access. Change-Id: I2030437636c77aea7cccda8efe050df4b77c15c7 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-21lib: Add ASan support to romstage on x86 archHarshit Sharma
This patch adds ASan support to romstage on x86 architecture. A Kconfig option is added to enable ASan in romstage. Compiler flags are updated. A memory space representing the shadow region is reserved in linker section. And a function call to asan_init() is added to initialize shadow region when romstage loads. Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-21lib: Add ASan support to ramstage on x86 archHarshit Sharma
This patch adds address sanitizer module to the library and reserves a linker section representing the shadow region for ramstage. Also, it adds an instruction to initialize shadow region on x86 architecture when ramstage is loaded. Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-20soc/amd/acpi: Move ACPI IVRS generation to corebootJason Glenesk
Add code for IVRS generation to coreboot. Publish coreboot generated structure rather than IVRS generated by FSP binary. Reference Doc: 48882_IOMMU_3.05_PUB.pdf BUG=b:155307433 TEST=Boot trembyle to shell and extract and compare IVRS tables and make sure they cover the same devices. Change-Id: I693f4399766c71c3ad53539634c65ba59afd0fe1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-08-19arch/x86/boot: Jump to payload in protected modePatrick Rudolph
* On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode. * Add a helper function to jump to arbitrary code in protected mode, similar to the real mode call handler. * Doesn't affect existing x86_32 code. * Add a macro to cast pointer to uint32_t that dies if it would overflow on conversion Tested on QEMU Q35 using SeaBIOS as payload. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-18elog: add ELOG_WAKE_SOURCE_GPIOAaron Durbin
Provide a GPIO-based wake source event for log caputre. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iaa15178a392f40156d8d10e9aedfd5a1e758eedb Reviewed-on: https://review.coreboot.org/c/coreboot/+/44532 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPEAaron Durbin
The wake source macro for GPE events was using 'GPIO'. However, current usage is really all GPEs. Therefore, provide clarity in the naming in order to allow for proper GPIO wake events that are separate from the ACPI GPE block. BUG=b:159947207 Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-18cpu/x86/smm/smm_stub: Add x86_64 supportPatrick Rudolph
Enable long mode in SMM handler. x86_32 isn't affected by this change. * Enter long mode * Add 64bit entry to GDT * Use x86_64 SysV ABI calling conventions for C code entry * Change smm_module_params' cpu to size_t as 'push' is native integer * Drop to protected mode after c handler NOTE: This commit does NOT introduce a new security model. It uses the same page tables as the remaining firmware does. This can be a security risk if someone is able to manipulate the page tables stored in ROM at runtime. USE FOR TESTING ONLY! Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
2020-08-17soc/intel/common: Move common HDA registers to <device/azalia_device.h>Elyes HAOUAS
Change-Id: I9ea191e5076e2f055405dc34d46dbbb8cfb0015e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44106 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17lib/imd_cbmem.c: Add a helper function to indicate that cbmem is readyArthur Heymans
This can be used in romstage in particular to know if dram is ready. Change-Id: I0231ab9c0b78a69faa762e0a97378bf0b50eebaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dramArthur Heymans
INVD is called below so if postcar is running in a cached environment it needs to happen. NOTE: postcar cannot execute in a cached environment if clflush is not supported! Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17soc/intel/jasperlake: Add IGD Device IDKrishna Prasad Bhat
Add IGD Device ID for Jasperlake. Reference is taken from Jasperlake EDS volume 1(Document Number: 613601). TEST=Build and boot Jasperlake platform. Change-Id: Iab3ba286f36afbf9533ac3cc62891fa390ca2441 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44000 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-15cpu/x86/smm: Introduce SMM module loader version 2Rocky Phagura
Xeon-SP Skylake Scalable Processor can have 36 CPU threads (18 cores). Current coreboot SMM is unable to handle more than ~32 CPU threads. This patch introduces a version 2 of the SMM module loader which addresses this problem. Having two versions of the SMM module loader prevents any issues to current projects. Future Xeon-SP products will be using this version of the SMM loader. Subsequent patches will enable board specific functionality for Xeon-SP. The reason for moving to version 2 is the state save area begins to encroach upon the SMI handling code when more than 32 CPU threads are in the system. This can cause system hangs, reboots, etc. The second change is related to staggered entry points with simple near jumps. In the current loader, near jumps will not work because the CPU is jumping within the same code segment. In version 2, "far" address jumps are necessary therefore protected mode must be enabled first. The SMM layout and how the CPUs are staggered are documented in the code. By making the modifications above, this allows the smm module loader to expand easily as more CPU threads are added. TEST=build for Tiogapass platform under OCP mainboard. Enable the following in Kconfig. select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON_BLOCK_SMM select SMM_TSEG select HAVE_SMI_HANDLER select ACPI_INTEL_HARDWARE_SLEEP_VALUES Debug console will show all 36 cores relocated. Further tested by generating SMI's to port 0xb2 using XDP/ITP HW debugger and ensured all cores entering and exiting SMM properly. In addition, booted to Linux 5.4 kernel and observed no issues during mp init. Change-Id: I00a23a5f2a46110536c344254868390dbb71854c Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10soc/intel/common: Include Alder Lake SATA controller device IDsSubrata Banik
Document Number: 619501, 619362 Change-Id: Id3440b415ca80edebb6880b8b48f6094ebea4ae4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-05drivers/genesyslogic/gl9763e: Add driver for Genesys Logic GL9763EBen Chuang
The device is a PCIe to eMMC bridge controller to be used in the Chromebook as the boot disk. The datasheet name is GL9763E and the revision is 02. The patch sets single request AXI, disables ASPM L0s and enables SSC. Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Change-Id: I158c79f5ac6e559f335b6b50092469c7b1646c56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-05include/device/azalia_device.h: Include <stdint.h>Elyes HAOUAS
This file only needs <stdint.h>. So replace <types.h> with <stdint.h>. Change-Id: Ib58532837941d5324b28bc2c607d70555ce9caee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44134 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05soc/intel/common: Include Alder Lake device IDsSubrata Banik
Add Alder Lake specific CPU, System Agent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 619362 Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-04src/lib: Remove unused function parameters in imd.cAnna Karas
Remove const struct imd *imd and const struct imdr *imdr parameters from the prototypes of imdr_entry_size(), imd_entry_size() and imd_entry_id() functions since they are not used anywhere. Signed-off-by: Anna Karas <aka@semihalf.com> Change-Id: I6b43e9a5ae1f1d108024b4060a04c57f5d77fb55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43999 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03assert.h: Try to evaluate assertions at compile timeJulius Werner
Many places in coreboot seem to like to do things like assert(CONFIG(SOME_KCONFIG)); This is somewhat suboptimal since assert() is a runtime check, so you don't see that this fails until someone actually tries to boot it even though the compiler is totally aware of it already. We already have the dead_code() macro to do this better: if (CONFIG(SOME_KCONFIG)) dead_code(); Rather than fixing all these and trying to carefully educate people about which type of check is more appropriate in what situation, we can just employ the magic of __builtin_constant_p() to automatically make the former statement behave like the latter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I06691b732598eb2a847a17167a1cb92149710916 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-03lib/string: Add standard strstr() functionJes Klinke
Adding implementation of standard library strstr() See https://review.coreboot.org/c/coreboot/+/43741 for context. Change-Id: I63e26e98ed2dd15542f81c0a3a5e353bb93b7350 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-31mb/ocp/deltalake: Update SMBIOS type 4 -- Processor InformationMorgan Jang
TEST=Execute "dmidecode -t 4" to check if the processor information is correct for Deltalake platform Change-Id: I5d075bb297f2e71a2545ab6ad82304a825ed7d19 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-30smbios: Fix type 17 for Windows 10Patrick Rudolph
The `GetPhysicallyInstalledSystemMemory` API call, at least on Windows 10, returns an error if SMBIOS tables are invalid. Various tools use this API call and don't operate correctly if this fails. For example, the "Intel Processor Diagnostic Tool" program is affected. Windows then guesses the physical memory size by accumulating entries from the firmware-provided memory map, which results in a total memory size that is slightly lower than the actual installed memory capacity. To fix this issue, add the handle to a type 16 entry to all type 17 entries. Add new fields to struct memory_info and fill them in Intel common code. Use the introduced variables to fill type 16 in smbios.c and provide a handle to type 17 entries. Besides keeping the current behaviour on intel/soc/common platforms, the type 16 table is also emitted on platforms that don't explicitly fill it, by using the existing fields of struct memory_info. Tested on Windows 10: The GetPhysicallyInstalledSystemMemory API call doesn't return an error anymore and the installed memory is now being reported as 8192 MiB. Change-Id: Idc3a363cbc3d0654dafd4176c4f4af9005210f42 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-28device: Add find_dev_nested_path helper functionRob Barnes
Add find_dev_nested_path helper function to simplify finding deeply nested devices. BUG=b:157580724 TEST=Find bluetooth device on dalboz Change-Id: I48fa5fcad0030fb6dcea97b9fc76e1d3d3f9b28f Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-28arch/x86/smbios: Bump to version 3.0Patrick Rudolph
Fill in the new fields introduced with version 3.0 and install the new entry point structure identified by _SM3_. Tested on Linux 5.6 using tianocore as payload: Still able to decode the tables without errors. Change-Id: Iba7a54e9de0b315f8072e6fd2880582355132a81 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-28PCI IDs: Add PCI ID for the realtek 5261Caveh Jalali
This adds the PCI ID of the realtek 5261 PCIe to SD Express card reader. BUG=b:161774205 TEST=none Change-Id: I4d5e6cfca59b02adc74a0c148281a92421fe209d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-28src: Never set ISA Enable on PCI bridgesAngel Pons
Looks like no one really knows what this bit would be useful for, nor when it would need to be set. Especially if coreboot is setting it even on PCI *Express* bridges. Digging through git history, nearly all instances of setting it on PCIe bridges comes from i82801gx, for which no reason was given as to why this would be needed. The other instances in Intel code seem to have been, unsurprisingly, copy-pasted. Drop all uses of this definition and rename it to avoid confusion. The negation in the name could trick people into setting this bit again. Tested on Asrock B85M Pro4, no visible difference. Change-Id: Ifaff29561769c111fb7897e95dbea842faec5df4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-07-28ACPI S3: Clean up resume pathKyösti Mälkki
Remove the obscure path in source code, where ACPI S3 resume was prohibited and acpi_resume() would return and continue to BS_WRITE_TABLES. The condition when ACPI S3 would be prohibited needs to be checked early in romstage already. For the time being, there has been little interest to have CMOS option to disable ACPI S3 resume feature. Change-Id: If5105912759427f94f84d46d1a3141aa75cbd6ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27include/rules.h: Add ENV_USER_SPACE definitionMartin Roth
This lets code that run in userspace notify coreboot of that fact so things that can't run in userspace can be excluded. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I4da414bc96cfcf0464125eddc6b3f3a7b4506fcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/43784 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26src/include: Remove unused 'include <stddef.h>'Elyes HAOUAS
Change-Id: I525eb58669d256286e8476b12174d37d1d9aa3bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src/include: Add missing includesElyes HAOUAS
Change-Id: I746ea7805bae553a146130994d8174aa2e189610 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth
The Kconfig lint tool checks for cases of the code using BOOL type Kconfig options directly instead of with CONFIG() and will print out warnings about it. It gets confused by these references in comments and strings. To fix it so that it can find the real issues, just update these as we would with real issues. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26arch/x86/smbios: Fix type4 for EDK2Patrick Rudolph
Mark the CPU as enabled and the socket as populated. EDK2 tests these flags before further reading this structure. Change-Id: Ic545bb47c502cb9d2352ba6d43eaed8c97229c02 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43703 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26smbios: Add Type19Patrick Rudolph
Implement type 19 by accumulating the DRAM dimm size found in cbmem's CBMEM_ID_MEMINFO structure. This seems common on x86 where the address space always starts at 0. At least EDK2 uses this table in the UI and shows 0 MB DRAM if not present. Change-Id: Idee8b8cd0b155e14d62d4c12893ff01878ef3f1c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-26smp/spinlock: Do not define barrier() globallyKyösti Mälkki
It's not stricly related to spinlocks. If defined, a better location should be found and the name collisions with other barrier() defined in nb/intel solved. Change-Id: Iae187b5bcc249c2a4bc7bee80d37e34c13d9e63d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43810 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26arch/x86: Move cpu_relax()Kyösti Mälkki
It's not related to spinlocks and the actual implementation was also guarded by CONFIG(SMP). With a single call-site in x86-specific code, empty stubs for other arch are currently not necessary. Also drop an unused included on a nearby line. Change-Id: I00439e9c1d10c943ab5e404f5d687d316768fa16 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43808 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26src/include: Remove unused 'include <stdint.h>'Elyes HAOUAS
Change-Id: I407474eac9f44f04036af7182714db7fdc4035f1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26device/device.h: Add `is_dev_enabled` functionAngel Pons
There are many places where we do this. Put it inside an inline function for convenience reasons. Change-Id: I5515a52458b6c78c1a723cb08e6471eb9bac9cd6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43871 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25src/include/ramdetect.h: Add missing includesElyes HAOUAS
Change-Id: I142f88aae67237ce6777f7f9e8849bae589beeb5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25soc/intel/tigerlake: Update Tiger Lake SA IDsDerek Huang
This patch updates Tiger Lake SA DID and report platform. According to doc #613584, remove PCI_DEVICE_ID_INTEL_TGL_ID_U_1 and add below definitions of SA ID for TGL-UP4 skus: TGL-UP4(Y) (4+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12h TGL-UP4(Y) (2+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02h Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43061 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24assert.h: Do not use __FILE__ nor __LINE__ on timeless buildsAngel Pons
When refactoring, one can move code around quite a bit while preserving reproducibility, unless there is an assert-style macro somewhere... As these macros use __FILE__ and __LINE__, just moving them is enough to change the resulting binary, making timeless builds rather useless. To improve reproducibility, do not use __FILE__ nor __LINE__ inside the assert-style macros. Instead, use hardcoded values. Plus, mention that timeless builds lack such information in place of the file name, so that grepping for the printed string directs one towards this commit. And for the immutable line number, we can use 404: line number not found :-) Change-Id: Id42d7121b6864759c042f8e4e438ee77a8ac0b41 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-20src: Make HAVE_CF9_RESET set the FADT reset registerAngel Pons
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as reset register in FADT. How unsurprising. We might as well use that information to automatically fill in the FADT accordingly. So, do it. To avoid having x86-specific code under arch-agnostic `acpi/`, create a new optional `arch_fill_fadt` function, and override it for x86 systems. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-18dptf: Fix scope of TCPU deviceTim Wawrzynczak
In the initial DPTF refactor, the scope of the TCPU device was incorrectly set as \_SB, instead of \_SB.PCI0. However, because of the way that the acpi_inject_dsdt() callback currently works (it injects contents before the dsdt.aml file), the Scope where the TCPU device lives (\_SB.PCI0) doesn't exist yet. Therefore, to avoid playing games with *when* things are defined in the DSDT, switch to defining all of the DPTF devices in the SSDT. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia4922b4dc6544d79d44d39e6ad18c6ab9fee0fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43529 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17device: Increase DEVICE_PATH_MAX to 40Furquan Shaikh
This change increases the maximum length of device path string to 40 characters to accommodate growing hierarchy of devices. TEST=Ensured that "\_SB.PCI0.LPCB.EC0.CREC.TUN0.RT58" is correctly added to SSDT. Change-Id: Id2ef71a32b26e366b56c652942a247de4889544a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-15PCI IDs: Add PCI ID for JSL DPTF/DTT PCI deviceTim Wawrzynczak
This PCI ID is required in order for JSL devices to perform SSDT generation for DPTF. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I42209d15bc4f1654814465ce1412576f7349dddc Reviewed-on: https://review.coreboot.org/c/coreboot/+/43421 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12soc/intel/tigerlake: Add new IGD deviceRavi Sarawadi
Add new IGD device ID for new Tigerlake SKU support. BUG=b:160394260 Branch=None TEST=build, boot and check IGD device is reported. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I1903d513b61655d0e939f80b0fd0108091fdd7e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 14:15:40 +0000