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2021-05-21soc/intel/common: Add Alder Lake device IDsSumeet R Pawnikar
Add Alder Lake specific Host and Graphics device IDs. As per latest document number: 619501, these IDs got an update. Change-Id: I548a903714ccc7470f1425ac67c0c66522437365 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54674 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela
Updated CPU ID and IGD ID for Alder Lake as per EDS. TEST=Code compilation works and coreboot is able to boot and identify new device Ids. Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14src/acpi: Add initial support for HMATJonathan Zhang
Add initial HMAT (Heterogeneous Memory Attribute Table) support based on ACPI spec 6.4 section 5.2.27. Add functions to create HMAT table (revision 2) and create HMAT Memory Proximity Domain Attribute (MPDA) Structure. TESTED=Simulated HMAT table creation on OCP DeltaLake server, dumped the HMAT table and exmained the content. HMAT table and one MPDA structure are added. OCP Delatake server is based on Intel CooperLake Scalable Processor which does not support CXL (Compute Express Link). Therefore solution level testing is not done. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14acpi: Add acpigen_write_thermal_zoneRaul E Rangel
BUG=b:186166365 TEST=Compiles Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icf88477143049119036c00276f9a01985dc0b4d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-12include/console: Fix FSP Notify phase postcodes discrepancySubrata Banik
List of changes: 1. Make the FSP notify phases name prior in comments section. 2. Fix discrepancies in FSP notify before and after postcode comments. 3. Add FSP notify postcode macros for after pci enumeration(0xa2) and ready to boot(0xa3) call. Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52894 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12include/console: Rename and update POST_ENTRY_RAMSTAGE postcodeSubrata Banik
Rename and update POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f to make the ramstage postcodes appear in an incremental order. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba Reviewed-on: https://review.coreboot.org/c/coreboot/+/52947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-12include/console: Fix duplicate entry of postcode 0x79Subrata Banik
Change POST_PRE_HARDWAREMAIN postcode value from 0x79 to 0x6e to avoid duplicate entry. Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-10*x86: fix x2apic mode boot issueWonkyu Kim
Fix booting issues on google/kahlee introduced by CB:51723. Update use inital apic id in smm_stub.S to support xapic mode error. Check more bits(LAPIC_BASE_MSR BIT10 and BIT11) for x2apic mode. TEST=Boot to OS and check apicid, debug log for CPUIDs cpuid_ebx(1), cpuid_ext(0xb, 0), cpuid_edx(0xb) etc Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ia28f60a077182c3753f6ba9fbdd141f951d39b37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-10device: Drop unused `uma_memory_{base,size}` globalsAngel Pons
These global variables are not used anywhere. Drop them. Change-Id: I3fe60b970153d913ae7b005257e2b53647d6f343 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53977 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10src: Drop "This file is part of the coreboot project" linesAngel Pons
Commit 6b5bc77c9b22c398262ff3f4dae3e14904c57366 (treewide: Remove "this file is part of" lines) removed most of them, but missed some files. Change-Id: Ib8e7ab26a74b52f86d91faeba77df3331531763f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-06drivers/pc80/rtc/option.c: Constrain API to integer valuesAngel Pons
None of the options accessed within coreboot is a string, and there are no guarantees that the code works as intended with them. Given that the current option API only supports integers for now, do not try to access options whose type is 's' (string). Change-Id: Ib67b126d972c6d55b77ea5ecfb862b4e9c766fe5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-06include/console: Align ramstage Boot State Machine postcodesSubrata Banik
This patch ensures all boot state machine postcodes are in right order. Move POST_ENTRY_RAMSTAGE macro definition after POST_BS_PAYLOAD_BOOT. Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52893 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak
With the recent switch to SMM module loader v2, the size of the SMM for module google/volteer increased to above 64K in size, and thus failed to install the permanent SMM handler. Turns out, the devicetree is all pulled into the SMM build because of elog, which calls `pci_dev_is_wake_source`, and is the only user of `struct device` in SMM. Changing this function to take a pci_devfn_t instead allows the linker to remove almost the entire devicetree from SMM (only usage left is when disabling HECI via SMM). BUG=b:186661594 TEST=Verify loaded program size of `smm.elf` for google/volteer is almost ~50% smaller. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-30mb/google: Move ECFW_RW setting for non-ChromeEC boardsKyösti Mälkki
The boolean is stored in ChromeOS NVS, not GNVS. Change-Id: I5c424a052d484228a456f8f0ad4fb0bed3165e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-30vc/google/chromeos: Refactor GNVS initKyösti Mälkki
Move the support code for filling ChromeOS GNVS from acpi/chromeos-gnvs.c to vc/google/chromeos/gnvs.c. Change-Id: I7e92206561812eb3dc69739df49b6c3a93853858 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50612 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30cpu/x86/msr: introduce helpers msr_read, msr_writeMichael Niewöhner
The existing helpers for reading/writing MSRs (rdmsr, wrmsr) require use of the struct `msr_t`, which splits the MSR value into two 32 bit parts. In many cases, where simple 32 bit or 64 bit values are written, this bloats the code by unnecessarly having to use that struct. Thus, introduce the helpers `msr_read` and `msr_write`, which take or return `uint64_t` values, so the code condenses to a single line or two, without having to deal with `msr_t`. Example 1: ~~~ msr_t msr = { .lo = read32((void *)(uintptr_t)0xfed30880), .hi = 0, }; msr.lo |= 1; wrmsr(0x123, msr); ~~~ becomes ~~~ uint32_t foo = read32((void *)(uintptr_t)0xfed30880); msr_write(0x123, foo | 1) ~~~ Example 2: ~~~ msr_t msr = rdmsr(0xff); uint64_t msr_val = (msr.hi << 32) | msr.lo; ~~~ becomes ~~~ uint64_t msr_val = msr_read(0xff); ~~~ Change-Id: I27333a4bdfe3c8cebfe49a16a4f1a066f558c4ce Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52548 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30src/acpi: Add APEI EINJ supportRocky Phagura
This adds full EINJ support with trigger action tables. The actual error injection functionality is HW specific. Therefore, HW specific code should call acpi_create_einj with an address where action table resides. The default params of the action table are filled out by the common code. Control is then returned back to the caller to modify or override default parameters. If no changes are needed, caller can simply add the acpi table. At runtime, FW is responsible for filling out the action table with the proper entries. The action table memory is shared between FW and OS. This memory should be marked as reserved in E820 table. Tested on Deltalake mainboard. Boot to OS, load the EINJ driver ( modprobe EINJ) and verify EINJ memory entries are in /proc/iomem. Further tested by injecting errors via the APEI file nodes. More information on error injection can be referenced in the latest ACPI spec. Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rocky Phagura
2021-04-28soc/intel: Add Z370, H310C and B365 device IDsAngel Pons
Intel document 335192-004 contains the PCI device IDs for Z370 and H310C, but lacks the ID for B365. The ID appears on some websites: https://linux-hardware.org/index.php?id=pci:8086-a2cc-1849-a2cc Change-Id: Iea3c435713c46854c5271fbc266f47ba4573db52 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52703 Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Add Kaby Lake PCH-U base device IDAngel Pons
Taken from Intel document 334658-003 (7th Generation Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel Processor Family I/O for U Quad Core Platforms, Datasheet - Volume 1 of 2). Change-Id: I1d48c8868e1e5d453d599ecec835938ce09935d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52702 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Rename 200-series PCH device IDsAngel Pons
The code name for these PCHs is Union Point, abbreviated as `UPT`. There are some 300-series Union Point PCHs (H310C, B365, Z370) which are meant to be paired with Coffee Lake CPUs instead of Skylake or Kaby Lake CPUs, and referring to them as `KBP` (Kaby Point, I guess) would be confusing. Tested with BUILD_TIMELESS=1, HP 280 G2 remains identical. Change-Id: I1a49115ae7ac37e76ce8d440910fb59926f34fac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52700 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23lib/espi_debug: Add espi_show_slave_peripheral_channel_configurationRaul E Rangel
Prints out the following: eSPI Slave Peripheral configuration: Peripheral Channel Maximum Read Request Size: 64 bytes Peripheral Channel Maximum Payload Size Selected: 64 bytes Peripheral Channel Maximum Payload Size Supported: 64 bytes Bus master: disabled Peripheral Channel: ready Peripheral Channel: enabled BUG=none TEST=boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7d598ee4f0f9d8ec0b37767e6a5a70288be2cb86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-23option.h: Drop type-unsafe {get,set}_option() APIAngel Pons
Change-Id: I5a9852b1fb66d609238ab7324f28a5e397c030ae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-22arch/x86/smbios: Let SMBIOS type 9 be able to write slot IDJingleHsuWiwynn
The slot ID can be passed in from the function caller but parsing slot ID from devicetree is not yet supported and would still be 0. Add Slot ID in SMBIOS type 9 for Delta Lake. Tested=Execute "dmidecode -t 9" to verify. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I9bf2e3b1232637a25ee595d08f8fbbc2283fcd5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-22ACPI: Fix the devices scope in the SATC structureJohn Zhao
This change adds the ATC_REQUIRED flag for the address translation cache indicator and fixes the devices scope entry in the SATC reporting structure. The SoC integrated devices in the specified PCI segment with address translation caches are a type of PCI Endpoint Device. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I57b3551f11502da48f3951da59d9426df5a40723 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-21acpi: Add acpigen_write_LPI_packageRaul E Rangel
Low Power Idle States defines additional information not present in the _CST. See ACPI Specification, Version 6.3 Section 8.4.4.3 _LPI. BUG=b:178728116, b:185787242 TEST=Boot guybrush and dump ACPI tables Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I4f5301b95ff8245facaf48e2fbd51cc82df2d8cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-21acpi: Add acpi_osc.hRaul E Rangel
See ACPI Specification, Version 6.3, Section 6.2.11 _OSC (Operating System Capabilities) We can add more UUIDs and capability flags in the future. BUG=b:178728116 TEST=Builds Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6e2ac1e1b47b284489932d6ed12db9d94e8d7310 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-21option.h: Introduce {get,set}_int_option() functionsAngel Pons
The {get,set}_option() functions are not type-safe: they take a pointer to void, without an associated length/size. Moreover, cmos_get_option() does not always fully initialise the destination value (it has no means to know how large it is), which can cause issues if the caller does not initialise the value beforehand. The idea behind this patch series is to replace the current type-unsafe API with a type-safe equivalent, and ultimately decouple the option API from CMOS. This would allow using different storage mechanisms with the same option system, maximising flexibility. Most, if not all users of get_option() have a value to fall back to, in case the option could not be read. Thus, get_int_option() takes a value to fall back to, which avoids repeating the same logic on call-sites. These new functions will be put to use in subsequent commits. Change-Id: I6bbc51135216f34518cfd05c3dc90fb68404c1cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21commonlib/region: Turn addrspace_32bit into a more official APIJulius Werner
We had the addrspace_32bit rdev in prog_loaders.c for a while to help represent memory ranges as an rdev, and we've found it useful for a couple of things that have nothing to do with program loading. This patch moves the concept straight into commonlib/region.c so it is no longer anchored in such a weird place, and easier to use in unit tests. Also expand the concept to the whole address space (there's no real need to restrict it to 32 bits in 64-bit environments) and introduce an rdev_chain_mem() helper function to make it a bit easier to use. Replace some direct uses of struct mem_region_device with this new API where it seems to make sense. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie4c763b77f77d227768556a9528681d771a08dca Reviewed-on: https://review.coreboot.org/c/coreboot/+/52533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-19cpu/x86/smm_loaderv2: Use the permanent stack top during relocationArthur Heymans
Use the same stack location during relocation as for the permanent handler. When the number of CPUs is too large the stacks during relocation don't fit inside the default SMRAM segment at 0x30000. Currently the code would just let the CPU stack base grow downwards outside of the default SMM segment which would corrupt lower memory if S3 is implemented. Also update the comment on smm_module_setup_stub(). Change-Id: I6a0a890e8b1c2408301564c22772032cfee4d296 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-15*x86: Support x2apic modeWonkyu Kim
Implement x2apic mode as existing code only supports apic mode. Use info from LAPIC_BASE_MSR (LAPIC_BASE_MSR_X2APIC_MODE) to check if apic mode or x2apic mode and implement x2apic mode according to x2apic specfication. Reference: https://software.intel.com/content/www/us/en/develop/download/intel-64-architecture-x2apic-specification.html BUG=None BRANCH=None TEST=boot to OS and check apic mode cat /proc/cpuinfo | grep "apicid" ex) can see apicid bigger than 255 apicid : 256 apicid : 260 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I0bb729b0521fb9dc38b7981014755daeaf9ca817 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51723 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14Rename do_printk() to printk()Nico Huber
The indirection seems unnecessary. The macros throw features like `-Wmisleading-indentation` off, though. Default build for QEMU/Q35 is unchanged. Change-Id: Ie4eab935a367b5ad6b38225c4973d41d9f70ef10 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-14console: Always add printf-format attribute to printk()Nico Huber
The attribute was missing in case the console is disabled. Change-Id: Iee23f6f4da61cd3637441705a8d3bbd2da7a33ca Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52231 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11spd.h: Move `DIMMx` macros to i440bx/raminit.hAngel Pons
These macros aren't needed anywhere else, so reduce their visibility. Change-Id: Ie8d14849b4fb86d34a841d4a13ee3bbb46f9f71c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52061 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09include/assert.h: Use mock_assert() for ENV_TEST targetsJakub Czapiga
Some tests have to be able to catch assertion errors. Adding CMocka mock_assert() enables that. Additionally fix test_imd_create_tiered_empty(), test_full_stack() and test_incorrectly_initialized_stack() by adding missing expect_assert_failure(). Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-06soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake MMaulik V Vaghela
Added new LPC and IGD device IDs for Alderlake M. Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c TEST=Check if platform information print is coming properly in coreboot Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06decompressor: Add CBFS_VERIFICATION supportJulius Werner
CBFS_VERIFICATION requires the CBFS metadata hash anchor to be linked into an uncompressed stage, but for platforms using COMPRESS_BOOTBLOCK, this is only the decompressor stage. The first CBFS accesses are made in the bootblock stage after decompression, so if we want to make CBFS_VERIFICATION work on those platforms, we have to pass the metadata hash anchor from the decompressor into the bootblock. This patch does just that. (Note that this relies on the decompressor data remaining valid in memory for as long as the metadata hash anchor is needed. This is always true even for OVERLAP_DECOMPRESSOR_ROMSTAGE() situations because the FMAP and CBFS metadata necessarily need to have finished verification before a new stage could be loaded.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2e6d7384cfb8339a24369eb6c01fc12f911c974e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52085 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06cbfs: Simplify cbfs_load_and_decompress() and stop exporting itJulius Werner
With the last external user to cbfs_load_and_decompress() gone, we can stop exporting this function to the rest of coreboot and make it local to cbfs.c. Also remove a couple of arguments that no longer really make a difference and fold the stage-specific code for in-place LZ4 decompression into cbfs_prog_stage_load(). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4b459650a28e020c4342a66090f55264fbd26363 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-06include/rules.h: Add ENV_TEST definitionJakub Czapiga
Some functions/macros like assert() require redefinition for testing purposes. ENV_TEST is introduced to make it possible without using bypass hacks. This patch also adds a global __TEST__ define to TEST_CFLAGS for all test targets in order to enable ENV_TEST. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ib8f2932902a73a7dbe181adc82cc18437abb48e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-04-06include/cbfsglue.h: Use BIOS_INFO for LOG macroWim Vervoorn
The ERROR() and LOG() macros both used BIOS_ERR as the error level. The messages generated by the LOG() macro are informational items. Change to BIOS_INFO to reflect that. BUG=N/A TEST=tested on facebook monolith Change-Id: I3827a7d65a9d70045a36fb8db4b2c129e1045122 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-04-06lib: Add obvious definition for `calloc`Tim Wawrzynczak
The calloc() function is useful in addition to malloc and friends, so add the obvious definition. Change-Id: I57a568e323344a97b35014b7b8bec16adc2fd720 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51949 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05cbfs: Make `mdata` argument to cbfs_allocator_t constJulius Werner
Right before CB:49334 was submitted, I changed the signature of cbfs_allocator_t function pointers to include another argument passing in the already loaded CBFS metadata (to allow for the rare edge case of allocators needing to read CBFS attributes). This interface is not meant to be able to modify the passed-in metadata, so to clarify that and prevent potential errors, we should declare the argument const. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7e3756490b9ad7ded91268c61797cef36c4118ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/52081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05device/dram/ddr3: Drop unused MRS helpersAngel Pons
These aren't used anywhere anymore. Change-Id: I4cf2fc0d07a772886e90fba4f66591a7b0a40e6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05spd.h: Remove unused definitionsAngel Pons
These definitions are unused and not particularly useful. Drop them. Change-Id: I40a824888701870b6713c1a16ab671c19b3770ae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51900 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05device/dram/ddr4.h: Align with DDR3 and DDR2Angel Pons
Drop unnecessary typedefs and rename DDR4-specific definitions to avoid name clashes, as done for DDR3 in earlier commits. This allows including and using both DDR3 and DDR4 headers in the same compilation unit. Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51898 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05include/spd_ddr2.h: Remove unused and redundant fileAngel Pons
DDR2-related definitions exist in `device/dram/ddr2` already. Change-Id: I509f728138327d8a0a88e4503235f05bf14aed20 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51897 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05device/dram/ddr3: Rename DDR3 SPD memory typesAngel Pons
To avoid name clashes with definitions for other DRAM generations, rename the enum type and values to contain `ddr3` or `DDR3`. Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05device/dram/ddr3: Get rid of useless typedefsAngel Pons
These typedefs are not necessary. Remove them, and rename some elements to avoid any confusion with other DRAM generations, such as DDR4. Change-Id: Ibe40f33372358262c540e371f7866b06a4ac842a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51895 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28ACPI: Add SATC structure for DMAR tableJohn Zhao
The SoC integrated address translation cache(SATC) reporting structure is added to Virtualization Technology for Directed I/O specification Rev3.2. This change adds an ACPI Name-Space Device Declaration structure SATC which has type 5 reporting structure. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I91d1384083c98b75bcbdddd9cc7b7a26fab25d9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51776 Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24acpi: Add acpigen_write_PRT* helpers for generating _PRT entriesTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia666bd0e5db40d7873532dc22bc89be9854b903a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-13 23:26:07 +0000