coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2012-04-25	Replace cache control magic numbers with symbols	Patrick Georgi
2012-04-16	S3 code in coreboot public folder.	zbao
2012-04-12	Add support for aligned allocation	Ron Minnich
2012-04-06	Fixes and Sandybridge support for lapic cpu init	Stefan Reinauer
2012-04-06	Add constants for fast path resume copying	Stefan Reinauer
2012-04-05	Fill out ChromeOS specific coreboot table extensions	Stefan Reinauer
2012-04-04	Add support to run SMM handler in TSEG instead of ASEG	Stefan Reinauer
2012-04-03	Add support for Intel Turbo Boost feature	Stefan Reinauer
2012-04-03	smbios: add support for onboard devices extended information	Stefan Reinauer
2012-04-02	Add a helper function to determine the number of enabled CPUs	Stefan Reinauer
2012-04-02	Align: Make sure 1 is treated as unsigned long instead of int	Stefan Reinauer
2012-03-30	Make MTRR min hole alignment 64MB	Duncan Laurie
2012-03-30	Add more timestamps in coreboot.	Stefan Reinauer
2012-03-30	Add timestamps for selfboot and acpi wake	Duncan Laurie
2012-03-30	Add TPM support to coreboot	Stefan Reinauer
2012-03-30	Add an option to keep the ROM cached after romstage	Stefan Reinauer
2012-03-29	Add infrastructure for global data in the CAR phase of boot	Gabe Black
2012-03-29	Detect whether the OXPCIE card is really present while in the ROM stage.	Gabe Black
2012-03-29	Add support for enabling PCIe Common Clock and ASPM	Duncan Laurie
2012-03-29	Refactor publishing CBMEM addresses through coreboot table.	Vadim Bendebury
2012-03-29	Add timestamp table pointer to the coreboot table.	Vadim Bendebury
2012-03-29	CBMEM CONSOLE: Add CBMEM type for console buffer.	Vadim Bendebury
2012-03-29	CBMEM CONSOLE: Add CBMEM console driver implementation.	Vadim Bendebury
2012-03-29	Increase CBMEM to accommodate larger console.	Vadim Bendebury
2012-03-28	Add cmos helper functions for reading/writing a dword	Duncan Laurie
2012-03-28	Add timestamp collecting to coreboot.	Vadim Bendebury
2012-03-28	Initialize CBMEM early.	Vadim Bendebury
2012-03-27	Add RDC R8610 PCI IDs.	Rudolf Marek
2012-03-16	xchg is atomic with side-effects	Patrick Georgi
2012-03-14	Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available	Gabe Black
2012-03-09	Increase size of the coreboot table area	Stefan Reinauer
2012-03-09	Add helper function to find a Local APIC by ID in the device tree.	Duncan Laurie
2012-03-09	move console includes to central console/console.h	Stefan Reinauer
2012-03-09	Add an implementation for the memchr library function	Gabe Black
2012-03-08	Unify Local APIC address definitions	Patrick Georgi
2012-02-16	pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids	Kerry Sheh
2012-02-16	AGESA F15: AGESA family15 model 00-0fh cpu wrapper	Kerry Sheh
2012-02-13	AMD Geode cpus: apply un-written naming rules	Kyösti Mälkki
2012-02-07	Add OPROM mapping support to coreboot	Stefan Reinauer
2012-01-24	RD890: pci_ids update	Kerry Sheh
2012-01-23	post code: Replaced hard-coded post code with macro	Vikram Narayanan
2012-01-12	lib: add ram_check_nodie	Sven Schnelle
2012-01-10	MTRR: get physical address size from CPUID	Sven Schnelle
2011-12-13	Fix CMOS handling for non-USE_OPTION_TABLE configuration	Patrick Georgi
2011-11-01	remove trailing whitespace	Stefan Reinauer
2011-11-01	Remove XIP_ROM_BASE	Patrick Georgi
2011-10-31	Fix usb debug dongle support	Sven Schnelle
2011-10-28	Get rid of AUTO_XIP_ROM_BASE	Patrick Georgi
2011-10-21	Extend coreboot table entry for serial ports	Stefan Reinauer
2011-10-21	Add macros for 64bit byte order swapping	Stefan Reinauer