summaryrefslogtreecommitdiff
path: root/src/include
AgeCommit message (Collapse)Author
2017-03-23cr50: add unmarshaling of vendor commands and process 'enable_update'Vadim Bendebury
The upcoming Cr50 firmware changes will require the AP to enable the previously downloaded Cr50 firmware update(s). A new vendor command (TPM2_CR50_SUB_CMD_TURN_UPDATE_ON) is used for that. The command accepts one parameter - a timeout value in range of 0 to 1000 ms. When processing the command the Cr50 checks if the alternative RO or RW image(s) need to be enabled, and if so - enables them and returns to the host the number of enabled headers. If the vendor command requested a non-zero timeout, the Cr50 starts a timer to trigger system reboot after the requested timeout expires. The host acts on the number of enabled headers - if the number is nonzero, the host prepares the device to be reset and waits for the Cr50 to reboot the device after timeout expires. This patch also adds more formal vendor command marshaling/unmarshaling to make future additions easier. BRANCH=gru,reef BUG=b:35580805 TEST=with the actual user of this code in the next patch verified that the cr50 update is enabled as expected. Change-Id: Ic76d384d637c0eeaad206e0a8242cbb8e2b19b37 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/18945 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-19cpu/x86: add a barrier with timeoutBora Guvendik
In case something goes wrong on one of the cpus, add the ability to use a barrier with timeout so that other cpus don't wait forever. Remove static from barrier wait and release. BUG=chrome-os-partner:59875 BRANCH=reef TEST=None Change-Id: Iab6bd30ddf7632c7a5785b338798960c26016b24 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/18107 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters Changed a few comments to reduce line length. File src/include/cpu/amd/vr.h was skipped. TEST=Build and run on Galileo Gen2 Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18687 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Add space after minus signLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: need consistent spacing around '-' (ctx:WxV) TEST=Build and run on Galileo Gen2 Change-Id: Ib4c2c0c19dee842b7cd4da11a47215dc2f124374 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18686 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Remove use of binary constantsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Avoid gcc v4.3+ binary constant extension: <...> TEST=Build and run on Galileo Gen2 Change-Id: Iab29c494060df3f60eff5317259e0fdbfea06f27 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18685 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Add spaces around :Lee Leahy
Fix the following error detected by checkpatch.pl: ERROR: spaces required around that ':' (ctx:ExV) TEST=Build and run on Galileo Gen2 Change-Id: Idb2ea29a6c7277b319e6600e8a9d7cb8285ae5df Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18684 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Fix indent for case labelsLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: switch and case should be at the same indent TEST=Build and run on Galileo Gen2 Change-Id: I92f00254c7fcb79a5ecd4ba5e19a757cfe5c11fa Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18683 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Move constants to the right hand sideLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Comparisons should place the constant on the right side of the test TEST=Build and run on Galileo Gen2 Change-Id: Id790e0034ea5c926fcaef95486319d6c0c936f28 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18682 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Remove space between function name and parametersLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Unnecessary space before function pointer arguments TEST=Build and run on Galileo Gen2 Change-Id: I2b56af20d5f74cc2625d3cb357fbb137bd440af0 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18660 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Move assignment out of if conditionLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: do not use assignment in if condition TEST=Build and run on Galileo Gen2 Change-Id: I911d528bd85afcd9f3837241494f13d1f9f283ab Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18659 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Remove unnecessary typecastLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Unnecessary typecast of c90 int constant TEST=Build and run on Galileo Gen2 Change-Id: I137efa55e945d1315322df2a38d70716a3807a1e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Move storage class to beginning of declarationLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: storage class should be at the beginning of the declaration The following storage class attribute is not detected by checkpatch.py: static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ section(".rodata.cbmem_init_hooks"))) = init_fn_; The following lines generates a false positive: (pound)define STATIC static src/include/cpu/amd/common/cbtypes.h:60: WARNING: storage class should be at the beginning of the declaration typedef asmlinkage void (*smm_handler_t)(void *); src/include/cpu/x86/smm.h:514: WARNING: storage class should be at the beginning of the declaration (pound)define MAYBE_STATIC static src/include/stddef.h:34: WARNING: storage class should be at the beginning of the declaration TEST=Build and run on Galileo Gen2 Change-Id: Ie087d38e6171b549b90e0b831050ac44746a1e14 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18657 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Remove space after function nameLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: space prohibited between function name and open parenthesis '(' TEST=Build and run on Galileo Gen2 Change-Id: I0ac30b32bab895ca72f91720eeae5a5067327247 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18656 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Fix space between type, * and variable nameLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "foo*bar" should be "foo *bar" TEST=Build and run on Galileo Gen2 Change-Id: I5a3ff8b92e3ceecb4ddf45d8840454d5310fc6b3 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18655 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2017-03-12src/include: Remove braces for single statementsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: I00b59f6a27c3acb393deaa763596363b7e958efd Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18654 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-12src/include: Open brace on same line as enum or structLee Leahy
Fix the following errors and warning detected by checkpatch.pl: ERROR: open brace '{' following enum go on the same line ERROR: open brace '{' following struct go on the same line ERROR: that open brace { should be on the previous line WARNING: missing space after struct definition TEST=Build and run on Galileo Gen2 Change-Id: I856235d0cc3a3e59376df52561b17b872b3416b2 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18653 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-12src/include: Remove spaces before tabsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: please, no space before tabs TEST=Build and run on Galileo Gen2 Change-Id: If60a58021d595289722d1d6064bea37b0b0bc039 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18652 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-12src/include: Remove spaces before ( and after )Lee Leahy
Fix the following error messages found by checkpatch.pl: ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' TEST=Build and run on Galileo Gen2 Change-Id: I2a9a0df640c51ff3efa83dde852dd6ff37ac3c06 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18651 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-10src/include: Add space after +Lee Leahy
Fix the following error detected by checkpatch.pl: ERROR: need consistent spacing around '+' (ctx:WxV) Test: Build and run on Galileo Gen2 Change-Id: Idd5f2a6d8a3c8db9c1a127ed75cec589929832e3 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18650 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10src/include: Add parenthesis around macrosLee Leahy
Fix the following error found by checkpatch.pl: ERROR: Macros with complex values should be enclosed in parentheses False positives are detected for attribute macros. An example is: ERROR: Macros with complex values should be enclosed in parentheses +#define BOOT_STATE_INIT_ATTR __attribute__ ((used, section (".bs_init"))) False positive also generated for macros for linker script files. An example is: ERROR: Macros with complex values should be enclosed in parentheses +#define CBFS_CACHE(addr, size) \ + REGION(cbfs_cache, addr, size, 4) \ + ALIAS_REGION(cbfs_cache, preram_cbfs_cache) \ + ALIAS_REGION(cbfs_cache, postram_cbfs_cache) False positives generated for assembly code macros. An example is: ERROR: Macros with complex values should be enclosed in parentheses +#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name ) False positive detected when macro includes multiple comma separated values. The following code is from src/include/device/azalia_device.h: #define AZALIA_SUBVENDOR(codec, val) \ (((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)), \ (((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff)), \ (((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff)), \ (((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff)) TEST=Build and run on Galileo Gen2 Change-Id: I6e3b6950738e6906851a172ba3a22e3d5af1e35d Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18649 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10src/include: Add space before (Lee Leahy
Fix the following error detected by checkpatch.py: ERROR: space required before the open parenthesis '(' TEST=Build and run on Galileo Gen2 Change-Id: I6969e63f750f327afff1a0efa1aab56d477af0df Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18645 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10device/dram/ddr2: Add common ddr2 spd decoderPatrick Rudolph
Decode DDR2 SPD similar to DDR3 SPD decoder to ease readability, reduce code complexity and reduce size of maintainable code. Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid compilation errors. Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18273 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2017-03-09vboot/tpm2: enable nvmem commits on cr50 when writing firmware secdataAaron Durbin
cr50 by default delays nvmem commits internally from the point of reset to accumulate change state. However, the factory process can put a board into dev mode through the recovery screen. This state is stored in the TPM's nvmem space. When the factory process is complete a disable_dev_request and battery_cutoff_request is performed. This leads to disabling the dev mode in TPM, but the battery is subsequently cut off so the nvmem contents never stick. Therefore, whenever antirollback_write_space_firmware() is called we know there was a change in secdata so request cr50 to immediately enable nvmem commits going forward. This allows state changes to happen immediately. The fallout from this is that when secdata is changed that current boot will take longer because every transaction that writes to TPM nvmem space will perform a write synchronously. All subsequent boots do not have that effect. It should also be noted that this approach to the implementation is a pretty severe layering violation. However, the current TPM APIs don't lend themselves well to extending commands or re-using code outside of the current routines which inherently assume all knowledge of every command (in conflict with vendor commands since those are vendor-specific by definition). BUG=b:35775104 BRANCH=reef TEST=Confirmed disablement of dev mode sticks in the presence of: crossystem disable_dev_request=1; crossystem battery_cutoff_request=1; reboot; Change-Id: I3395db9cbdfea45da1f5cb994c6570978593b944 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18681 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09elog: Add all EC event codesFurquan Shaikh
Add the missing EC event codes in elog.h and correct the event code value for RECOVERY_HWREINIT. Change-Id: If9fb319cce1e4acce4b3d7c3a39365986856a9b4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18693 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09src/include: Remove space after &Lee Leahy
Fix the following error detected by checkpatch.pl: ERROR: space prohibited after that '&' (ctx:ExW) TEST=Build and run on Galileo Gen2 Change-Id: Ied8b4c00fc57a35ed4d649264a5ff1b8dcc6a1cd Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18648 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09src/include: Add space after commaLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: space required after that ',' (ctx:VxV) TEST=Build and run on Galileo Gen2 Change-Id: I297bfc3d03dc95b471d3bb4b13803e81963841b5 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18647 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09src/include: Indent code using tabsLee Leahy
Fix the following error and warning detected by checkpatch.pl: ERROR: code indent should use tabs where possible WARNING: please, no spaces at the start of a line TEST=Build and run on Galileo Gen2 Change-Id: I487771b8f4d7e104457116b772cd32df5cd721a6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18646 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09src/include: Add do { } while(0) around macrosLee Leahy
Fix the following error detected by checkpatch.py: ERROR: Macros with multiple statements should be enclosed in a do - while loop False positives are generated when assembly code is used in a macro. An example is: ERROR: Macros with multiple statements should be enclosed in a do - while loop +#define post_code(value) \ + movb $value, %al; \ + outb %al, $CONFIG_POST_IO_PORT False positives are also generated for linker script include files. An example is: ERROR: Macros with multiple statements should be enclosed in a do - while loop +#define SET_COUNTER(name, addr) \ + _ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \ + . = addr; False positives are also generated for attribute macros. An example is: ERROR: Macros with multiple statements should be enclosed in a do - while loop +#define DISABLE_TRACE_ON_FUNCTION __attribute__ ((no_instrument_function)); TEST=Build and run on Galileo Gen2 Change-Id: I88abf96579e906f6962d558a3d09907f07d00b1c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18644 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09src/include: Move trailing statements to next lineLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: trailing statements should be on next line TEST=Build and run on Galileo Gen2 Change-Id: I169f520db6f62dfea50d2bb8fb69a8e8257f86c7 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18643 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09src/include: Fix unsigned warningsLee Leahy
Fix warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' BRANCH=none BUG=None TEST=Build and run on Galileo Gen2 Change-Id: I23d9b4b715aa74acc387db8fb8d3c73bd5cabfaa Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18607 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-08AMD geode: Avoid conflicting main() declarationKyösti Mälkki
Declaration of main in cpu/amd/car.h conflicts with the definition of main required for x86/postcar.c in main_decl.h. Change-Id: I19507b89a1e2ecf88ca574c560d4a9e9a3756f37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18615 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-07console: Enable printk for ENV_LIBAGESAKyösti Mälkki
Messages from AGESA proper are additionally controlled by various IDS parameters in board/OptionsIds.h file. Change-Id: I83e975d37ad2bdecb09c483ecae71c0ed6877731 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18545 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-07Stage rules.h: Add ENV_LIBAGESAKyösti Mälkki
Definition is required to enable use of printk() from AGESA proper. Change-Id: I6666a003c91794490f670802d496321ffb965cd3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18544 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-07elog: Fix duplicate event typeDuncan Laurie
The current elog implementation has two event types defined for 0xa7, apparently the result of divergent coreboot trees on chromium where some events were added to ARM systems but not upstreamed until later. Fix this by moving ELOG_TYPE_THERM_TRIP to be 0xab, since the current elog parsing code in chromium is using ELOG_TYPE_SLEEP for 0xa7. BUG=b:35977516 TEST=check for proper "CPU Thermal Trip" event when investigating a device that is unexpectedly powering down. Change-Id: Idfa9b2322527803097f4f19f7930ccbdf2eccf35 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18579 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-01src/include: Include stdint.h since struct dimm_info uses itBarnali Sarkar
struct dimm_info has all the parameter types defined in stdint.h file. So including it. BUG=none BRANCH=none TEST=Build and boot KBLRVP Change-Id: I707523749ecf415e993b460f9613eae7be859c34 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18471 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20arch/x86: add functions to generate random numbersRobbie Zhang
Using x86 RDRAND instruction, two functions are supplied to generate a 32bit or 64bit number. One potential usage is the sealing key generation for SGX. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve to generate a 64bit random number. Change-Id: I50cbeda4de17ccf2fc5efc1fe04f6b1a31ec268c Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18362 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-16device: Add scan_generic_bus supportFurquan Shaikh
scan_smbus routine does not perform any smbus specific operation. Thus, rename the routine to scan_generic_bus so that it can be used by other buses like SPI. Add a wrapper scan_smbus to allow other users of smbus scan to continue working as before. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I8ca1a2b7f2906d186ec39e9223ce18b8a1f27196 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18363 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-16device: Add a new "SPI" device typeFurquan Shaikh
Add support for a new "SPI" device type in the devicetree to bind a device on the SPI bus. Allow device to provide chip select number for the device as a parameter. Add spi_bus_operations with operation dev_to_bus which allows SoCs to define a translation method for converting "struct device" into a unique SPI bus number. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully. Change-Id: I86f09516d3cddd619fef23a4659c9e4eadbcf3fa Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18340 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-02-16spi: Add function callback to get configuration of SPI busFurquan Shaikh
Add a new callback to spi_ctrlr structure - get_config - to obtain configuration of SPI bus from the controller driver. Also, move common config definitions from acpi_device.h to spi-generic.h BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I412c8c70167d18058a32041c2310bc1c884043ce Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18337 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-10ddr3 spd: move accessor code into lib/spd_bin.cPatrick Georgi
It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-10ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs()Patrick Georgi
Since it checks for DDR3 style checksums, it's a more appropriate name. Also make its configuration local for a future code move. Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18264 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-06devtree: Drop unused parameter show_devs_tree() callKyösti Mälkki
Change-Id: I14c044bb32713ef4133bce8a8238a2bc200c4959 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18085 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-04x86/acpi: Add VFCT tablePatrick Rudolph
Add VFCT table to provide PCI Optiom Rom for AMD graphic devices. Useful for GNU Linux payloads and embedded dual GPU systems. Tested on Lenovo T500 with AMD RV635 as secondary gpu. Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422 Reviewed-on: https://review.coreboot.org/18192 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-12google/chromeos: disable platform hierarchy on resume for TPM2Aaron Durbin
On Chrome OS devices that use TPM2 parts the platform hierarchy is disabled by the boot loader, depthcharge. Since the bootloader isn't involved in resuming a suspended machine there's no equivalent action in coreboot to disable the platform hierarchy. Therefore, to ensure consistent state in resume the platform hierarchy in the TPM2 needs to be disabled as well. For systems that resume using the firmware the platform hierarchy is disabled when utilizing TPM2 devices. BUG=chrome-os-partner:61097 BRANCH=reef TEST=Suspend and resume. Confirmed 'stop trunksd; tpmc getvf; start trunksd' shows that phEnable is 0. Change-Id: I060252f338c8fd68389273224ee58caa99881de8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18096 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-09chromeos: Implement locating and decoding wifi sar data from VPDRobbie Zhang
A VPD entry "wifi_sar" needs to be created which contains a heximal encoded string in length of 40 bytes. get_wifi_sar_limits() function retrieves and decodes the data from the VPD entry, which would later be consumed by platform code. BUG=chrome-os-partner:60821 TEST=Build and boot lars and reef Change-Id: I923b58a63dc1f8a7fdd685cf1c618b2fdf4e7061 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/17958 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-06arch/x86: fix cmos post logging in non romcc bootblockAaron Durbin
cmos_post_init() is called in src/arch/x86/bootblock_simple.c, and that function is reponsible for bootstrapping the cmos post register contents. Without this function being called none of the cmos post functionality works correctly. Therefore, add a call to lib/bootblock.c which the C_ENVIRONMENT_BOOTBLOCK SoCs use. BUG=chrome-os-partner:61546 Change-Id: I2e3519f2f3f2c28e5cba26b5811f1eb0c2a90572 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18043 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-23spi: Get rid of SPI_ATOMIC_SEQUENCINGFurquan Shaikh
SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. 4. Provide helper functions for common cases like supporting only 2 vectors at a time, supporting n vectors at a time, default vector operation to cycle through all SPI op vectors one by one. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17681 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-15smbios.h: add missing SKU field to type3 tableMatt DeVillier
The type3 SMBIOS table has a non-optional SKU field at the end, which causes a parsing error when missing. Add but do not populate it. Change-Id: I988d0626b8680740697e1db58eb6d0b87874bfde Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17851 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-15lib/cbmem: allow anyone to use cbmem_possibly_online()Aaron Durbin
The cbmem_possibly_online() is a helpful construct. Therefore, push it into cbmem.h so other users can take advantage of it. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: If5a1c7815ed03874dcf141014b8ffefb82b7cc92 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17868 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-13pc80: Move set_boot_successful()Kyösti Mälkki
Don't implement arch or driver -specific code under lib/, Change-Id: If75980ec5efc622582e2b5e124ad0e7ee3fa39a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17793 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 02:11:06 +0000