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2016-07-14tpm2: implement locking firmware rollback counterVadim Bendebury
TPM1.2 is using the somewhat misnamed tlcl_set_global_lock() command function to lock the hardware rollback counter. For TPM2 let's implement and use the TPM2 command to lock an NV Ram location (TPM2_NV_WriteLock). BRANCH=none BUG=chrome-os-partner:50645 TEST=verified that TPM2_NV_WriteLock command is invoked before RO firmware starts RW, and succeeds. Change-Id: I52aa8db95b908488ec4cf0843afeb6310dc7f38b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 2f859335dfccfeea900f15bbb8c6cb3fd5ec8c77 Original-Change-Id: I62f22b9991522d4309cccc44180a5ebd4dca488d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/358097 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Darren Krahn <dkrahn@chromium.org> Reviewed-on: https://review.coreboot.org/15638 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-13tpm2: use pcr0 dependent nvram space policy definitionsVadim Bendebury
The TPM2 specification allows defining NV ram spaces in a manner that makes it impossible to remove the space until a certain PCR is in a certain state. This comes in handy when defining spaces for rollback counters: make their removal depend on PCR0 being in the default state. Then extend PCR0 to any value. This guarantees that the spaces can not be deleted. Also, there is no need t create firmware and kernel rollback spaces with different privileges: they both can be created with the same set of properties, the firmware space could be locked by the RO firmware, and the kernel space could be locked by the RW firmware thus providing necessary privilege levels. BRANCH=none BUG=chrome-os-partner:50645, chrome-os-partner:55063 TEST=with the rest of the patches applied it is possible to boot into Chrome OS maintaining two rollback counter spaces in the TPM NV ram locked at different phases of the boot process. Change-Id: I889b2c4c4831ae01c093f33c09b4d98a11d758da Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 36317f5e85107b1b2e732a5bb2a38295120560cd Original-Change-Id: I69e5ada65a5f15a8c04be9def92a8e1f4b753d9a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/358094 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15635 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-12SPD: Add CAS latency 2Elyes HAOUAS
CAS latency = 2 support added for DDR2. Change-Id: I08d72a61c27ff0eab19e500a2f547a5e946de2f0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15439 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-12vboot2: tpm2 factory initialization.Vadim Bendebury
This patch adds a TPM2 specific path in the vboot2 initialization sequence when the device is turned on in the factory for the first time, namely two secure NVRAM spaces are created, with different access privileges. The higher privilege space can be modified only be the RO firmware, and the lower privilege space can be modified by both RO and RW firmware. The API is being modified to hide the TPM implementation details from the caller. Some functions previously exported as global are in fact not used anywhere else, they are being defined static. BRANCH=none BUG=chrome-os-partner:50645 TEST=when this code is enabled the two secure spaces are successfully created during factory initialization. Original-Commit-Id: 5f082d6a9b095c3efc283b7a49eac9b4f2bcb6ec Original-Change-Id: I917b2f74dfdbd214d7f651ce3d4b80f4a18def20 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353916 Original-Reviewed-by: Bill Richardson <wfrichar@chromium.org> Original-Reviewed-by: Darren Krahn <dkrahn@chromium.org> squashed: mock tpm: drop unused functions safe_write() and safe_define_space() functions are defined in secdata_mock.c, but not used in mocked TPM mode. The actual functions have been redefined as static recently and their declarations were removed from src/include/antirollback.h, which now causes compilation problems when CONFIG_VBOOT2_MOCK_SECDATA is defined. Dropping the functions from secdata_mock.c solves the problem. BRANCH=none BUG=none TEST=compilation in mock secdata mode does not fail any more. Original-Commit-Id: c6d7824f52534ecd3b02172cb9078f03e318cb2b Original-Change-Id: Ia781ce99630d759469d2bded40952ed21830e611 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356291 Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Change-Id: Icb686c5f9129067eb4bb3ea10bbb85a075b29955 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15571 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-11tpm2: implement tlcl layerVadim Bendebury
This is the first approximation of implementing TPM2 support in coreboot. It is very clearly incomplete, some of the larger missing pieces being: - PCR(s) modification - protection NVRAM spaces from unauthorized deletion/modification. - resume handling - cr50 specific factory initialization The existing TPM1.2 firmware API is being implemented for TPM2. Some functions are not required at all, some do not map fully, but the API is not yet being changed, many functions are just stubs. An addition to the API is the new tlcl_define_space() function. It abstracts TMP internals allowing the caller to specify the privilege level of the space to be defined. Two privilege levels are defined, higher for the RO firmware and lower for RW firmware, they determine who can write into the spaces. BRANCH=none BUG=chrome-os-partner:50645 TEST=with the rest of the patches applied Kevin/Gru devices can initialize and use firmware and kernel spaces Change-Id: Ife3301cf161ce38d61f11e4b60f1b43cab9a4eba Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: bcc8e62604c705798ca106e7995a0960b92b3f35 Original-Change-Id: Ib340fa8e7db51c10e5080973c16a19b0ebbb61e6 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353914 Original-Commit-Ready: Martin Roth <martinroth@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15569 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-10intel post-car: Consolidate choose_top_of_stack()Kyösti Mälkki
Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15463 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-07lib/gpio: add pullup & pulldown gpio_base2_value() variantsAaron Durbin
Provide common implementations for gpio_base2_value() variants which configure the gpio for internal pullups and pulldowns. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: I9be8813328e99d28eb4145501450caab25d51f37 Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15557 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-02gpio: Add support for translating gpio_t into ACPI pinDuncan Laurie
Add a function for an SOC to define that will allow it to map the SOC-specific gpio_t value into an appropriate ACPI pin. The exact behavior depends on the GPIO implementation in the SOC, but it can be used to provide a pin number that is relative to the community or bank that a GPIO resides in. Change-Id: Icb97ccf7d6a9034877614d49166bc9e4fe659bcf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15512 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01lib: remove ulzma()Aaron Durbin
That function is no longer used. All users have been updated to use the ulzman() function which specifies lengths for the input and output buffers. Change-Id: Ie630172be914a88ace010ec3ff4ff97da414cb5e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15526 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-06-29lib/nhlt: drop nhlt_soc_add_endpoint()Aaron Durbin
The nhlt_soc_add_endpoint() is no longer used. Drop its declaration. Change-Id: I3b68471650a43c5faae44bde523abca7ba250a34 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15489 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-29lib/nhlt: add helper functions for adding endpointsAaron Durbin
In order to ease the porting of supporting NHLT endpoints introduce a nhlt_endpoint_descriptor structure as well as corresponding helper functions. Change-Id: I68edaf681b4e60502f6ddbbd04de21d8aa072296 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15486 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-24soc/intel/common: Add prototype for global_reset() resetAndrey Petrov
Add prototype for global_reset() that some SoCs need to provide. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I8afe076b6f4f675b3c6a3ec0e4dd69f950baa4ef Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15333 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24lib: Add real-time-clock functionsSimon Glass
Add functions to convert between seconds and a struct rtc_time. Also add a function that can display the time on the console. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) with future commits and after setting RTC on the EC: boot on gru into linux shell, check firmware log: localhost ~ # grep Date: /sys/firmware/log Date: 2016-06-20 (Monday) Time: 18:01:44 Then reboot ~10 seconds and check again: localhost ~ # grep Date: /sys/firmware/log Date: 2016-06-20 (Monday) Time: 18:01:54 Change-Id: Id148ccb7a18a05865b903307358666ff6c7b4a3d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3b02dbcd7d9023ce0acabebcf904e70007428d27 Original-Change-Id: I344c385e2e4cb995d3a374025c205f01c38b660d Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351782 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24SPD: Add DRAM devices typesElyes HAOUAS
Add SDRAM or module types to byte 2. Change-Id: Id6e654a3a714c164bc9a7fbd9ab3e2f3c44ca5ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15265 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24SPD: fix DDR3 SDRAM memory module typesElyes HAOUAS
Correct the definitions for 16b and 32b SO-DIMM modules. Regarding JEDEC Standard No. 21-C Annex K: Serial Presence Detect for DDR3 SDRAM Modules (2014), the hex values used for 16b-SO-DIMM is 0x0c and for 32b-SO-DIMM module type is 0x0d Change-Id: I9210ac3409a4aaf55a0f6411d5960cfdca05068d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15262 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24SPD: fix and add DDR2 SDRAM memory module typesElyes HAOUAS
Correct the definitions and add 72b-SO-CDIMM and 72b-SO-RDIMM Change-Id: I33532e30f45f6c8c0eb6d47b0bea87689d2d9a1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15204 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24spd: Add module voltage for 1.8VElyes HAOUAS
Add SSTL 1.8 V Interface Level as specified in JEDEC_DDR2_SPD_Specification_ Rev1.3, page 10. Change-Id: I0112a85f557826b629109e212dbbc752aeda305d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15202 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-22soc/intel/common/acpi: Add _PTS, _WAK methodsHannah Williams
Change-Id: I72f894fd14bf0e333d9fda970397a3c82de598c3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15121 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22cpu/cpu.h: Change guard around function declarationsKyösti Mälkki
This file is pulled for x86 bootblock builds using ROMCC, which would choke on struct bus. Change-Id: Ie3566cd5cfc4b4e0e910b47785449de81a07b9ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15274 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
Without RELOCATABLE_RAMSTAGE have WB cache large enough to cover the greatest ramstage needs, as there is no benefit of trying to accurately match the actual need. Choose this to be bottom 16MiB. With RELOCATABLE_RAMSTAGE write-back cache of low ram is only useful for bottom 1MiB of RAM as a small part of this gets used during SMP initialisation before proper MTRR setup. Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22intel: Drop old romstage main() without asmlinkageKyösti Mälkki
Change-Id: I0d471766fdf46f6e61ac692fc98730a2429f981f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15234 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20include/device/dram/ddr3: Add additional frequenciesPatrick Rudolph
IvyBridge memory controller supports more frequencies than SandyBridge. Required for future patches. Change-Id: I0bcb670c20407ec0aec20bae85c4cbe6ccc44b16 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15182 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-06-18intel: Fix romstage main() with asmlinkageKyösti Mälkki
Backport from haswell. Change-Id: I585639f8af47bd1d8c606789ca026c6d2d0cc785 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15225 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-18AMD boards: Fix romstage main() declarationKyösti Mälkki
Boards incorrectly used intel include file for AMD board. Change-Id: I6d3172d1aa5c91c989a6ef63066a7cd6f70013f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15232 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
Change-Id: I3c517fc55dd333b1a457324f1d69aeb6f70acec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15197 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
This is more of ACPI S3 resume and x86 definition than CBMEM. Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15190 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-14Added CL7 supportElyes HAOUAS
according to "JEDEC_DDR2_SPD_Specification_Rev1.3.pdf" Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3) page 16 and page 60, CL7 support added Change-Id: I22aaf064ab8767755f74dfdb44e32d13fc61b2c4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/14976 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-12bootblock: Declare common bootblock_pre_c_entry routineLee Leahy
Enable uses of a common bootblock_pre_c_entry routine. Pass in TSC value as a uint64_t value. TEST=Build for amenia and Galileo Gen2 Change-Id: I8be2e079ababb2cf1f9b7e6293f93e7c778761a1 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15124 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <lpleahyjr@gmail.com>
2016-06-09lib: Add asmlinkage attribute to bootblock_main_with_timestampLee Leahy
Add asmlinkage to bootblock_main_with_timestamp so that it may be called directly from the assembly code. TEST=Build for Amenia and Galileo Gen2 Change-Id: Iefb8e5c1ddce2ec495b9272966b595d5adcebc1c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15125 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09device: i2c: Add support for I2C bus operationsDuncan Laurie
In order to support doing bus operations on an I2C device that is described in the devicetree there needs to be some linkage of the device and the existing opaque I2C controller bus number. This is provided in a similar fashion to the existing SMBUS operations but modified to fit within the existing I2C infrastructure. Variants of the existing I2C helper functions are provided that will obtain the bus number that corresponds to this device by looking for the SOC-provided I2C bus operation structure to provide a function that will make that translation. For example an SOC using a PCI I2C controller at 0:15.0 could use: soc/intel/.../i2c.c: static int i2c_dev_to_bus(struct device *dev) { if (dev->path.pci.devfn == PCI_DEVFN(0x15, 0)) return 0; return -1; } static struct i2c_bus_operation i2c_bus_ops = { .dev_to_bus = &i2c_dev_to_bus } static struct device_operations i2c_dev_ops = { .ops_i2c_bus = &i2c_bus_ops ... } With an I2C device on that bus at address 0x1a described in the tree: devicetree.cb: device pci 15.0 on # I2C0 chip drivers/i2c/sample device i2c 1a.0 on end end end That driver can then do I2C transactions with the device object without needing to know that the SOC-specific bus number that this I2C device lives on is "0". For example it could read a version value from register address 0 with a byte transaction: drivers/i2c/sample/sample.c: static void i2c_sample_enable(struct device *dev) { uint8_t ver; if (!i2c_dev_readb(dev, 0x00, &ver)) printk(BIOS_INFO, "I2C %s version 0x02x\n", dev_path(dev), ver); } Change-Id: I6c41c8e0d10caabe01cc41da96382074de40e91e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15100 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02SMBIOS: Implement SKU fieldKyösti Mälkki
Leave it for the platform to fill in the string. Change-Id: I7b4fe585f8d1efc8c9743f0d8b38de1f98124aab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14996 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-02wrdd: Export WRDD info in the headerDuncan Laurie
Export the WRDD spec revision and WiFi domain type in the header file so it can be used to generate ACPI tables by wifi drivers. Change-Id: I3222eca723c52fe74a004aa7bac7167264249fd1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15018 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28acpi_device: Add support for writing ACPI I2C descriptorsDuncan Laurie
Add required definitions to describe an ACPI I2C bus and a method to write the I2cSerialBus() descriptor to the SSDT. This will be used by device drivers to describe their I2C resources to the OS. The devicetree i2c device can supply the address and 7 or 10 bit mode as well as indicate the GPIO controller device, and the bus speed can be fixed or configured by the driver. chip.h: struct drivers_i2c_generic_config { enum i2c_speed bus_speed; }; generic.c: void acpi_fill_ssdt_generator(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; struct acpi_i2c i2c = { .address = dev->path->i2c.device, .mode_10bit = dev->path.i2c.mode_10bit, .speed = config->bus_speed ? : I2C_SPEED_FAST, .resource = acpi_device_path(dev->bus->dev) }; ... acpi_device_write_i2c(&i2c); ... } devicetree.cb: device pci 15.0 on chip drivers/i2c/generic device i2c 10.0 on end end end SSDT.dsl: I2cSerialBus (0x10, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.I2C0", 0, ResourceConsumer) Change-Id: I598401ac81a92c72f19da0271af1e218580a6c49 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14935 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25soc/intel/common: Add common smihandler codeHannah Williams
Provide default handler for some SMI events. Provide the framework for extracting data from SMM Save State area for processors with SMM revision 30100 and 30101. The SOC specific code should initialize southbridge_smi with event handlers. For SMM Save state handling, SOC code should implement get_smm_save_state_ops which initializes the SOC specific ops for SMM Save State handling. Change-Id: I0aefb6dbb2b1cac5961f9e43f4752b5929235df3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-21gpio: Add a function to map GPIO to ACPI pathDuncan Laurie
Add a new function "gpio_acpi_path()" that can be implemented by SoC/board code to provide a mapping from a "gpio_t" pin to a controller by returning the ACPI path for the controller that owns this particular GPIO. This is implemented separately from the "acpi_name" handler as many SOCs do not have a specific device that handles GPIOs (or may have many devices and the only way to know which is the opaque gpio_t) and the current GPIO library does not have any association with the device tree. If not implemented (many SoCs do not implement the GPIO library abstraction at all in coreboot) then the default handler will return NULL and the caller knows it cannot determine this reliably. Change-Id: Iaa0ff6c8c058f00cddf0909c4b7405a0660d4cfb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14842 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-21device: Add an ACPI device name and path concept to devicesDuncan Laurie
Add a function to "struct device_operations" to return the ACPI name for the device, and helper functions to find this name (either from the device or its parent) and to build a fully qualified ACPI path from the root device. This addition will allow device drivers to generate their ACPI AML in the SSDT at boot, with customization supplied by devicetree.cb, instead of needing custom DSDT ASL for every mainboard. The root device acpi_name is defined as "\\_SB" and is used to start the path when building a fully qualified name. This requires SOC support to provide handlers for returning the ACPI name for devices that it owns, and those names must match the objects declared in the DSDT. The handler can be done either in each device driver or with a global handler for the entire SOC. Simplified example of how this can be used for an i2c device declared in devicetree.cb with: chip soc/intel/skylake # "\_SB" (from root device) device domain 0 on # "PCI0" device pci 19.2 on # "I2C4" chip drivers/i2c/test0 device i2c 1a.0 on end # "TST0" end end end end And basic SSDT generating code in the device driver: acpigen_write_scope(acpi_device_scope(dev)); acpigen_write_device(acpi_device_name(dev)); acpigen_write_string("_HID", "TEST0000"); acpigen_write_byte("_UID", 0); acpigen_pop_len(); /* device */ acpigen_pop_len(); /* scope */ Will produce this ACPI code: Scope (\_SB.PCI0.I2C4) { Device (TST0) { Name (_HID, "TEST0000") Name (_UID, 0) } } Change-Id: Ie149595aeab96266fa5f006e7934339f0119ac54 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14840 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-21hexstrtobin: Add a library function to decode ASCII hex into binaryDuncan Laurie
This function will turn a string of ASCII hex characters into an array of bytes. It will ignore any non-ASCII-hex characters in the input string and decode up to len bytes of data from it. This can be used for turning MAC addresses or UUID strings into binary for storage or further processing. Sample usage: uint8_t buf[6]; hexstrtobin("00:0e:c6:81:72:01", buf, sizeof(buf)); acpigen_emit_stream(buf, sizeof(buf)); Change-Id: I2de9bd28ae8c42cdca09eec11a3bba497a52988c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14837 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-19lib/bootblock: Provide mechanism to pass in an early timestampAlexandru Gagniuc
This is useful, for example, in the bootblock, when a timestamp is available which predates the call to main() in lib/bootblock.c Change-Id: I17bb0add9f2d8721504b2e534dd6904d1201989c Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-05-16sconfig: Add a new generic device typeDuncan Laurie
Add support for a basic generic device in the devicetree to bind to a device that does not have a specific bus, but may need to be described in tables for the operating system. For instance some chips may have various GPIO connections that need described but do not fall under any other device. In order to support this export the basic 'scan_static_bus()' that can be used in a device_operations->scan_bus() method to scan for the generic devices. It has been possible to get a semi-generic device by using a fake PNP device, but that isn't really appropriate for many devices. Also Re-generate the shipped files for sconfig. Use flex 2.6.0 to avoid everything being rewritten. Clean up the local paths that leak into the generated configs. Change-Id: If45a5b18825bdb2cf1e4ba4297ee426cbd1678e3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14789 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-16sconfig: Add 10bit addressing mode to i2c device typeDuncan Laurie
Use the second token for an i2c device entry in devicetree.cb to indicate if it should use 10-bit addressing or 7-bit. The default if not provided is to use 7-bit addressing, but it can be changed to 10-bit addressing with the ".1" suffix. For example: chip drivers/i2c/generic device i2c 3a.1 on end end Change-Id: I1d81a7e154fbc040def4d99ad07966fac242a472 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14788 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-09drivers/uart: Enable override for input clock dividerLee Leahy
Allow the platform to override the input clock divider by adding the uart_input_clock_divider routine. This routine combines the baud-rate oversample divider with any other input clock divider. The default routine returns 16 which is the standard baud-rate oversampling value. A platform may override this default "weak" routine by providing a new routine and selecting UART_OVERRIDE_INPUT_CLOCK_DIVIDER. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Ieb6453b045d84702b8f730988d0fed9f253f63e2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-06cpu/x86/mp_init: reduce exposure of internal implementationAaron Durbin
With all users converted to using the mp_ops callbacks there's no need to expose that surface area. Therefore, keep it all within the mp_init compilation unit. Change-Id: Ia1cc5326c1fa5ffde86b90d805b8379f4e4f46cd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14598 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-04lib/reg_script: Add display supportLee Leahy
Add the ability to enable the display of the script: * Added REG_SCRIPT_COMMAND_DISPLAY to enable and disable display output * Added context values to manage display support * display_state - Updated by the command to enable or disable display * display_features - May be updated by step routine to control what the step displays for register and value * display_prefix - Prefix to display before register data * Added REG_SCRIPT_DISPLAY_ON and REG_SCRIPT_DISPLAY_OFF macros to control the display from the register script * Added REG_SCRIPT_DISPLAY_REGISTER and REG_SCRIPT_DISPLAY_VALUE as two features of the common display. With these features enabled the following is output: * Write: <optional prefix> register <-- value * Read: <optional prefix> register --> value TEST=Build and run on Galileo Gen2 Change-Id: If0d4d61ed8ef48ec20082b327f358fd1987e3fb9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14553 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-04cpu/x86: combine multiprocessor and SMM initializationAaron Durbin
In order to reduce code duplication provide a common flow through callback functions that performs the multiprocessor and optionally SMM initialization. The existing MP flight records are utilized but a common flow is provided such that the chipset/cpu only needs to provide a mp_ops structure which has callbacks to gather info and provide hooks at certain points in the sequence. All current users of the MP code can be switched over to this flow since there haven't been any flight records that are overly complicated and long. After the conversion has taken place most of the surface area of the MP API can be hidden away within the compilation unit proper. Change-Id: I6f70969631012982126f0d0d76e5fac6880c24f0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14557 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04cpu/x86/smm_module_loader: always build with SMM module supportAaron Durbin
The SMM module loader code was guarded by CONFIG_SMM_TSEG, however that's not necessary. It's up to the chipset to take advantage of the SMM module loading. It'll get optimized out if the code isn't used anyway so just expose the declarations. Change-Id: I6ba1b91d0c84febd4f1a92737b3d7303ab61b343 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14560 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-02cpu/x86/mp_init: remove unused callback argumentsAaron Durbin
The BSP and AP callback declarations both had an optional argument that could be passed. In practice that functionality was never used so drop it. Change-Id: I47fa814a593b6c2ee164c88d255178d3fb71e8ce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14556 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-04-30lib/reg_script: Allow multiple independent handlersLee Leahy
Remove the platform_bus_table routine and replace it with a link time table. This allows the handlers to be spread across multiple modules without any one module knowing about all of the handlers. Establish number ranges for both the SOC and mainboard. TEST=Build and run on Galileo Gen2 Change-Id: I0823d443d3352f31ba7fa20845bbf550b585c86f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14554 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-30lib/regscript: Add exclusive-or (xor) supportLee Leahy
Add xor support which enables toggling of a bit: * REG_SCRIPT_COMMAND_RXW enum value * REG_*_RXW* macros to support using REG_SCRIPT_COMMAND_RXW * REG_*_XOR* macros to support using REG_SCRIPT_COMMAND_RXW * reg_script_rxw routine to perform and/xor operation * case in reg_script_run_step to call reg_script_rxw TEST=Build and run on Galileo Gen2 Change-Id: I50a492c7c2643df5dc2d2fa7113e3722c1e480c7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14495 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-21lib: add common write_tables() implementationAaron Durbin
In order to de-duplicate common patterns implement one write_tables() function. The new write_tables() replaces all the architecture-specific ones that were largely copied. The callbacks are put in place to handle any per-architecture requirements. Change-Id: Id3d7abdce5b30f5557ccfe1dacff3c58c59f5e2b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14436 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21lib/coreboot_table: add architecture hooks for adding tablesAaron Durbin
Add a architecture specific function, arch_write_tables(), that allows an architecture to add its required tables for booting. This callback helps write_tables() to be de-duplicated. Change-Id: I805c2f166b1e75942ad28b6e7e1982d64d2d5498 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14435 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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