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2013-02-08armv7: Use same console initialization procedure for all ARM stagesHung-Te Lin
Use same console initialization procedure for all ARM stages (bootblock, romstage, and ramstage): #include <console/console.h> ... console_init() ... printk(level, format, ...) Verified to boot on armv7/snow with console messages in all stages. Change-Id: Idd689219035e67450ea133838a2ca02f8d74557e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2301 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-08console: Only print romstage messages with EARLY_CONSOLE enabled.Hung-Te Lin
Revise console source file dependency (especially for EARLY_CONSOLE) and interpret printk/console_init according to EARLY_CONSOLE setting (no-ops if EARLY_CONSOLE is not defined). Verified to boot on x86/qemu and armv7/snow. Disabling EARLY_CONSOLE correctly stops romstage messages on x86/qemu (armv7/snow needs more changes to work). Change-Id: Idbbd3a26bc1135c9d3ae282aad486961fb60e0ea Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2300 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08console: Revise serial console configuration names.Hung-Te Lin
The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06replace uchar and uint with standard types in generic i2c headerDavid Hendricks
Change-Id: Ie72985bb5291bcef2e837a2f4f2ec929a0c086ce Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2290 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05exynos: de-duplicate UART header contentDavid Hendricks
Some header content got duplicated during the initial porting effort. This moves generic UART header stuff to exynos5-common and leaves exynos5250 #defines in the AP-specific UART header. Change-Id: Ifb6289d7b9dc26c76ae4dfcf511590b3885715a3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2285 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-04add gpio.h for generic GPIO-related definitionsDavid Hendricks
This adds /src/include/gpio.h which currently contains generic GPIO enums for type (in/out/alt) and 3-state logic. The header was originally written for another FOSS project (code.google.com/p/mosys) and thus the BSD license. Change-Id: Id1dff69169e8b1ec372107737d356b0fa0d80498 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2265 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30Extend CBFS to support arbitrary ROM source media.Hung-Te Lin
Summary: Isolate CBFS underlying I/O to board/arch-specific implementations as "media stream", to allow loading and booting romstage on non-x86. CBFS functions now all take a new "media source" parameter; use CBFS_DEFAULT_MEDIA if you simply want to load from main firmware. API Changes: cbfs_find => cbfs_get_file. cbfs_find_file => cbfs_get_file_content. cbfs_get_file => cbfs_get_file_content with correct type. CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM, the ROM may come from USB, UART, or SPI -- any serial devices and not available for memory mapping. To support these devices (and allowing CBFS to read from multiple source at the same time), CBFS operations are now virtual-ized into "cbfs_media". To simplify porting existing code, every media source must support both "reading into pre-allocated memory (read)" and "read and return an allocated buffer (map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*" provides simple memory mapping simulation. Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA is defined for CBFS functions to automatically initialize a per-board default media (CBFS will internally calls init_default_cbfs_media). Also revised CBFS function names relying on memory mapped backend (ex, "cbfs_find" => actually loads files). Now we only have two getters: struct cbfs_file *entry = cbfs_get_file(media, name); void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type); Test results: - Verified to work on x86/qemu. - Compiles on ARM, and follow up commit will provide working SPI driver. Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2182 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-12Implement GCC code coverage analysisStefan Reinauer
In order to provide some insight on what code is executed during coreboot's run time and how well our test scenarios work, this adds code coverage support to coreboot's ram stage. This should be easily adaptable for payloads, and maybe even romstage. See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for more information. To instrument coreboot, select CONFIG_COVERAGE ("Code coverage support") in Kconfig, and recompile coreboot. coreboot will then store its code coverage information into CBMEM, if possible. Then, run "cbmem -CV" as root on the target system running the instrumented coreboot binary. This will create a whole bunch of .gcda files that contain coverage information. Tar them up, copy them to your build system machine, and untar them. Then you can use your favorite coverage utility (gcov, lcov, ...) to visualize code coverage. For a sneak peak of what will expect you, please take a look at http://www.coreboot.org/~stepan/coreboot-coverage/ Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2052 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11cbmem: replace pointer type by uint64_tStefan Reinauer
Since coreboot is compiled into 32bit code, and userspace might be 32 or 64bit, putting a pointer into the coreboot table is not viable. Instead, use a uint64_t, which is always big enough for a pointer, even if we decide to move to a 64bit coreboot at some point. Change-Id: Ic974cdcbc9b95126dd1e07125f3e9dce104545f5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2135 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04Change "VERSION*" to more determined name "CBFS_HEADER_VERSION*".Hung-Te Lin
The 'VERSION' in CBFS header file is confusing and may conflict when being used in libpayload. Change-Id: I24cce0cd73540e38d96f222df0a65414b16f6260 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2098 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-04make early serial console support more genericDavid Hendricks
This patch makes pre-RAM serial init more generic, particularly for platforms which do not necessarily need cache-as-RAM in order to use the serial console and do not have a standard 8250 serial port. This adds a Kconfig variable to set romstage-* for very early serial console init. The current method assumes that cache-as-RAM should enable this, so to maintain compatibility selecting CACHE_AS_RAM will also select EARLY_SERIAL_CONSOLE. The UART code structure needs some rework, but the use of ROMCC, romstage, and then ramstage makes things complex. uart.h now includes all .h files for all uarts. All 2 of them. This is actually a simplifying change. Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2086 Tested-by: build bot (Jenkins)
2013-01-03Fix strcpy()Stefan Reinauer
'nough said. It was broken since 2006. Change-Id: I312ac07eee65d6bb8567851dd38064c7f51b3bd2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2062 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-29import i2c header from u-bootDavid Hendricks
This just imports a header. We may wish to modify the i2c interface and/or unify it with the smbus interface we currently have. Change-Id: I314f3aef62be936456c6c3e164a3db2c473b8792 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2079 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-19Add back dummy free()Stefan Reinauer
GNU CC coverage needs free() and it's highly desirable to leave the code as genuine as possible. Change-Id: I4c821b9d211ef7a8e7168dc5e3116730693999c6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2051 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-12Claim the SPI bus before writes if the IMC ROM is presentMartin Roth
The SB800 and Hudson now support adding the IMC ROM which runs from the same chip as coreboot. When the IMC is running, write or erase commands sent to the spi bus will fail, and the IMC will die. To fix this, we send a request to the IMC to stop fetching from the SPI rom while we write to it. This process (in one form or another) is required for writes to the SPI bus while the IMC is running. Because the IMC can take up to 500ms to respond every time we claim the bus, this patch tries to keep the number of times we need to do that to a minimum. We only need to claim the bus on writes, and using a counter for the semaphore allows us to call in once to claim the bus at the beginning of a number of transactions and it will stay claimed until we release it at the end of the transactions. Claim() - takes up to 500ms hit claim() - no delay erase() release() claim() - no delay write() release() Release() Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1976 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-12Fix UART8250 console prototypesStefan Reinauer
and disable IO mapped UARTs on ARMV7 per default Change-Id: I712c4677cbc8519323970556718f9bb6327d83c8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2021 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-12-08stddef.h: move to generic codeStefan Reinauer
stddef.h should be fairly generic across all platforms we'd want to support, so let's move it to generic code. Change-Id: I580c9c9b54f62fadd9ea97115933e16ea0b13ada Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2007 Tested-by: build bot (Jenkins)
2012-12-08WIP: Add support for non-8250 built-in UARTsStefan Reinauer
Change-Id: I5b412678bb8993633b3a610315d298cb20c705f3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2011 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08cbfs_core.h: support for ARMv7 CBFS master headerStefan Reinauer
Change-Id: I59626200b4a92d90b46625f8dcc2ed28e6376e46 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2008 Tested-by: build bot (Jenkins)
2012-12-06Unify assembler function handlingStefan Reinauer
Instead of adding regparm(0) to each assembler function called by coreboot, add an asmlinkage macro (like the Linux kernel does) that can be different per architecture (and that is empty on ARM right now) Change-Id: I7ad10c463f6c552f1201f77ae24ed354ac48e2d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1973 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30Make set_boot_successful depend on PC80_SYSTEMStefan Reinauer
Set_boot_successful depends on CMOS parts that non-PC80 platforms do not have. For now, make the current path depend on CONFIG_PC80_SYSTEM, and make the alternative empty. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I68cf63367c8054d09a7a22303e7c04fb35ad0153 Reviewed-on: http://review.coreboot.org/1954 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30Add multi-architecture support to cbfstoolDavid Hendricks
This is an initial re-factoring of CBFS code to enable multiple architectures. To achieve a clean solution, an additional field describing the architecture has to be added to the master header. Hence we also increase the version number in the master header. Change-Id: Icda681673221f8c27efbc46f16c2c5682b16a265 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1944 Tested-by: build bot (Jenkins)
2012-11-27Add initialization hook for chipsNico Huber
Add an init() function to the chip_operations which will be called before bus enumeration. This allows to disable unused devices before they get enumerated. Change-Id: I63dd9cbfc7b5995ccafb7bf7a81dc71fc67906a0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1623 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-20Unify use of bool config variablesStefan Reinauer
e.g. -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS This will make it easier to switch over to use the config_enabled() macro later on. Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-19mc146818rtc: disable RTC before writing to nvramPatrick Georgi
In principle this isn't necessary. However there's a byte (or several) outside the first 14 bytes that are part of the RTC, and require locking (century/altCentury). Since their location is mostly unknown, guard writes properly. Change-Id: I847cd4efa92722e8504d29feaf7dbfa5c5244b4e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1868 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-14SMM: Avoid use of global variables in SMI handlerDuncan Laurie
Using global variables with the TSEG is a bad idea because they are not relocated properly right now. Instead make the variables static and add accessor functions for the rest of SMM to use. At the same time drop the tcg/smi1 pointers as they are not setup or ever used. (the debug output is added back in a subsequent commit) Change-Id: If0b2d47df4e482ead71bf713c1ef748da840073b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1764 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Restore GNVS pointer in the resume pathDuncan Laurie
The SMM GNVS pointer is normally updated only when the ACPI tables are created, which does not happen in the resume path. In order to restore this pointer it needs to be available at resume time. The method used to locate it at creation time cannot be used again as that magic signature is overwritten with the address itself. So a new CBMEM ID is added to store the 32bit address so it can be found again easily. A new function is defined to save this pointer in CBMEM which needs to be called when the ACPI tables are created in each mainboard when write_acpi_tables() is called. The cpu_index variable had to be renamed due to a conflict when cpu/cpu.h is added for the smm_setup_structures() prototype. Change-Id: Ic764ff54525e12b617c1dd8d6a3e5c4f547c3e6b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1765 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Provide MRC with a console printing callback functionVadim Bendebury
Let memory initialization code use the coreboot romstage console. This simplifies the code and makes sure that all output is available in /sys/firmware/log. The pei_data structure is modified to allow passing the console output function pointer. Romstage console_tx_byte() is used for this purpose. Change-Id: I722cfcb9ff0cf527c12cb6cac09d77ef17b588e0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1823 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Clean up stack checking codeStefan Reinauer
Several small improvements of the stack checking code: - move the CPU0 stack check right before jumping to the payload and out of hardwaremain (that file is too crowded anyways) - fix prototype in lib.h - print size of used stack - use checkstack function both on CPU0 and CPU1-x - print amount of stack used per core Signed-off-by: Stefan Reinauer <reinauer@google.com> Test: Boot coreboot on Link, see the following output: ... CPU1: stack: 00156000 - 00157000, lowest used address 00156c68, stack used: 920 bytes CPU2: stack: 00155000 - 00156000, lowest used address 00155c68, stack used: 920 bytes CPU3: stack: 00154000 - 00155000, lowest used address 00154c68, stack used: 920 bytes ... Jumping to boot code at 1110008 CPU0: stack: 00157000 - 00158000, lowest used address 00157af8, stack used: 1288 bytes Change-Id: I7b83eeee0186559a0a62daa12e3f7782990fd2df Reviewed-on: http://review.coreboot.org/1787 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Add method for delaying adding of timestampsStefan Reinauer
In hardwaremain() we can't add timestamps before we actually reinitialized the cbmem area. Hence we kept the timestamps in an array and added them later. This is ugly and intrusive and helped hiding a bug that prevented any timestamps to be logged in hardwaremain() when coming out of an S3 resume. The problem is solved by moving the logic to keep a few timestamps around into the timestamp code. This also gets rid of a lot of ugly ifdefs in hardwaremain.c Change-Id: I945fc4c77e990f620c18cbd054ccd87e746706ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1785 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Pass the CPU index as a parameter to startup.Ronald G. Minnich
This addition is in support of future multicore support in coreboot. It also will allow us to remove some asssembly code. The CPU "index" -- i.e., its order in the sequence in which cores are brought up, NOT its APIC id -- is passed into the secondary start. We modify the function to specify regparm(0). We also take this opportunity to do some cleanup: indexes become unsigned ints, not unsigned longs, for example. Build and boot on a multicore system, with pcserial enabled. Capture the output. Observe that the messages Initializing CPU #0 Initializing CPU #1 Initializing CPU #2 Initializing CPU #3 appear exactly as they do prior to this change. Change-Id: I5854d8d957c414f75fdd63fb017d2249330f955d Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1820 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-12ELOG: Support for non-memory mapped flashDuncan Laurie
If the event log is stored in flash that is not memory mapped then it must use the SPI controller to read from the flash device instead of relying on memory accesses. In addition a new CBMEM ID is added to keep an resident copy of the ELOG around if needed. The use of CBMEM for this is guarded by a new CONFIG_ELOG_CBMEM config option. This CBMEM buffer is created and filled late in the process when the SMBIOS table is being created because CBMEM is not functional when ELOG is first initialized. The downside to using CBMEM is that events added via the SMI handler at runtime are not reflected in the CBMEM copy because I don't want to let the SMM handler write to memory outside the TSEG region. In reality the only time we add runtime events is at kernel shutdown so the impact is limited. Test: 1) Test with CONFIG_ELOG_CBMEM enabled to ensure the event log is operational and SMBIOS points to address in CBMEM. The test should involve at least on reboot to ensure that the kernel is able to write events as well. > mosys -l smbios info log | grep ^address address | 0xacedd000 > mosys eventlog list 0 | 2012-10-10 14:02:46 | Log area cleared | 4096 1 | 2012-10-10 14:02:46 | System boot | 478 2 | 2012-10-10 14:02:46 | System Reset 3 | 2012-10-10 14:03:33 | Kernel Event | Clean Shutdown 4 | 2012-10-10 14:03:34 | System boot | 479 5 | 2012-10-10 14:03:34 | System Reset 2) Test with CONFIG_ELOG_CBMEM disabled to ensure the event log is operational and SMBIOS points to memory mapped flash. The test should involve at least on reboot to ensure that the kernel is able to write events as well. > mosys -l smbios info log | grep ^address address | 0xffbf0000 > mosys eventlog list 0 | 2012-10-10 14:33:17 | Log area cleared | 4096 1 | 2012-10-10 14:33:18 | System boot | 480 2 | 2012-10-10 14:33:18 | System Reset 3 | 2012-10-10 14:33:35 | Kernel Event | Clean Shutdown 4 | 2012-10-10 14:33:36 | System boot | 481 5 | 2012-10-10 14:33:36 | System Reset Change-Id: I87755d5291ce209c1e647792227c433dc966615d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1776 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12SPI: Fix and enable Fast Read supportDuncan Laurie
- Fix handling of 5-byte Fast Read command in the ICH SPI driver. This fix is ported from the U-boot driver. - Allow CONFIG_SPI_FLASH_NO_FAST_READ to be overridden by defining a name for the bool in Kconfig and removing the forced select in southbridge config - Fix use of CONFIG_SPI_FLASH_NO_FAST_READ in SPI drivers to use #if instead of #ifdef - Relocate flash functions in SMM so they are usable. This really only needs to happen for read function pointer since it uses a global function rather than a static one from the chip, but it is good to ensure the rest are set up correctly as well. Change-Id: Ic1bb0764cb111f96dd8a389d83b39fe8f5e72fbd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1775 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Fix gcc-4.7 building problem.Han Shen
Applied function attribute to function definition to avoid 'conflicting type' warning. Function declaration is in src/include/cpu.h void secondary_cpu_init(unsigned int cpu_index)__attribute__((regparm(0))); But function definition in lapic_cpu_init.c is missing the "__attribute__" part. Change-Id: Idb7cd00fda5a2d486893f9866920929c685d266e Signed-off-by: Han Shen <shenhan@google.com> Reviewed-on: http://review.coreboot.org/1784 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-12Define post codes for OS boot and resumeDuncan Laurie
And move the pre-hardwaremain post code to 0x79 so it comes before hardwaremain at 0x80. Emit these codes from ACPI OS resume vector as well as the finalize step in bd82x6x southbridge. Change-Id: I7f258998a2f6549016e99b67bc21f7c59d2bcf9e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-09Prevent inclusion of tsc.h when not neededVadim Bendebury
src/include/timestamp.h is an interface describing timestamp storage in coreboot. Exporting this interface is complicated by inclusion of tsc.h which is needed only for the API and is not used in structure definitions. Including this dependency only when needed fixes the problem. Change-Id: Ie6b1460b1dab0f5b5781cb5a9fa89a1a52aa9f17 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1753 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-09ELOG: Add EC events to elog headerDuncan Laurie
These events were initially for Chrome EC but they can be applied to any EC. Change-Id: I0eba9dbe8bde506e7f9ce18c7793399d40e6ab3b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1746 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09mc146818rtc: Remove the hyphen to build on NetBSD and DarwinZheng Bao
http://netbsd.gw.com/cgi-bin/man-cgi?date++NetBSD-current The NetBSD manual tells us the date in NetBSD doesn't take any flags to enable or disable padding in the format. By default, date pads numeric fields with zeroes. This will convert the number to octal one. So add "0x" to convert it to BCD directly. Change-Id: Icd44312acf01b8232f1da1fbaa70630d09007b40 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1804 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-08Log unexpected post code from the previous bootDuncan Laurie
Read out the post code from the previous boot and log it if the code is not one of the expected values. Test: 1) interrupt the boot of the system, this is easiest with warm reset button when servo is attached 2) check the event log with mosys 65 | 2012-09-09 12:32:11 | Last post code in previous boot | 0x9d Change-Id: Id418f4c0cf005a3e97b8c63de67cb9a09bc57384 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1744 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08Add support for storing POST codes in CMOSDuncan Laurie
This will use 3 bytes of CMOS to keep track of the POST code for the current boot while also leaving a record of the previous boot. The active bank is switched early in the bootblock. Test: 1) clear cmos 2) reboot 3) use "mosys nvram dump" to verify that the first byte contains 0x80 and the second byte contains 0xF8 4) powerd_suspend and then resume 5) use "mosys nvram dump" to verify that the first byte contains 0x81 and the second byte contains 0xFD Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08elog: add extended management engine eventDuncan Laurie
We are seeing ME disabled and ME error events on some devices and this extended info can help with debug. Also fix a potential issue where if the log does manage to get completely full it will never try to shrink it because the only call to shrink the log happens after a successful event write. Add a check at elog init time to shrink the log size. Change-Id: Ib81dc231f6a004b341900374e6c07962cc292031 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-07SPI: opmenu special case for WREN as atomic prefixDuncan Laurie
The code that attempts to use the opmenu needs to have a special case for write enable now that it is handled as an atomic prefix and not as a standalone opcode. To test, ensure that runtime SPI write via ELOG is successful by checking the event log for a kernel shutdown reason code: 5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown 6 | 2012-08-27 11:09:50 | System boot | 26 7 | 2012-08-27 11:09:50 | System Reset Change-Id: I527638ef3e2a5ab100192c5be6e6b3b40916295a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1710 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07RTC: Write build date in BCD when clearing RTC CMOSDuncan Laurie
Check the RTC on boot after RTC battery failure and ensure that the reported build date matches what is reported: > grep ^rtc /proc/driver/rtc rtc_time : 01:00:21 rtc_date : 2012-08-16 Change-Id: If23f436796754c68ae6244ef7633ff4fa0a93603 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1709 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07EC: Prepare to read and log last post code from previous bootDuncan Laurie
(elog portion, support in EC code pending) - Use a new EC command to read the last post code from the previous boot - If the post code is not well-known final boot or resume code then log it Change-Id: Id6249e9a182243eb87c777edd56f48de72125e77 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1703 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07Add POST code for "All devices initialized"Stefan Reinauer
Right now we only had a post code for "All devices enabled" which was emitted at the wrong time (after the device initialize stage rather than the device enable stage) Change-Id: Iee82bff020de844c7095703f8d6521953003032c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1693 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
Compose the name from Kconfig strings instead. As the field is for debug print use only, a minor change in the output should do no harm. The strings no longer include word "Mainboard". Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06Add name field for deviceKyösti Mälkki
The constant field "name" in chip_operations is common to multiple different devices within a chip and cannot reflect the actual device as found on the platform. The intention is that a driver sets dev->name as part of the device enumeration sequence with the detected hardware type and revision. The field is for debug print use only. Change-Id: Ib7bf90ba3c618ad0cb715d80d6a937ceaae0adcf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-05Overhaul speedstep codeNico Huber
This adds proper support for turbo and super-low-frequency modes. Calculation of the p-states has been rewritten and moved into an extra file speedstep.c so it can be used for non-acpi stuff like EMTTM table generation. It has been tested with a Core2Duo T9400 (Penryn) and a Core Duo T2300 (Yonah) processor. Change-Id: I5f7104fc921ba67d85794254f11d486b6688ecec Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1658 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
We had only some MSR definitions in there, which are used in speedstep related code. I think speedstep.h is the better and less confusing place for these. Change-Id: I1eddea72c1e2d3b2f651468b08b3c6f88b713149 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1655 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-29Drop get_smbios_data from chip_operationsKyösti Mälkki
We only want to add data once per device. Using the one in chip_operations is not very usable anyway, as different devices under the same chip directory would need to output entirely different sets of data. Change-Id: I96690c4c699667343ebef44a7f3de1f974cf6d6d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1492 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
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