coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2012-07-24	Add code to read Intel microcode from CBFS	Vadim Bendebury
2012-07-24	Add support for HM70 and NM70 LPC bridge	Stefan Reinauer
2012-07-24	Add uartmem_init prototype.	Marc Jones
2012-07-24	RTC: Add defines for standard clock offsets	Duncan Laurie
2012-07-24	Remove unused free() function	Stefan Reinauer
2012-07-24	SPI flash layer: remove unused function spi_flash_free()	Stefan Reinauer
2012-07-20	Allow shutting down internal graphics if plugin graphics are preferred	Patrick Georgi
2012-07-16	Change uma_resource() to use new type IORESOURCE_UMA_FB.	Kyösti Mälkki
2012-07-16	Define global uma_memory variables	Kyösti Mälkki
2012-07-16	Add global uma_resource()	Kyösti Mälkki
2012-07-13	MPTAPLE: generate from devicetree.cb	Sven Schnelle
2012-07-12	Lenovo X60: correct SDHCI write protect polarity	Jonathan A. Kollasch
2012-07-09	SMBIOS: Add Type 38 (IPMI) data structure	Sven Schnelle
2012-07-05	PCI Type2 config must die	Ronald G. Minnich
2012-07-04	Intel cpus: Extend cache to cover complete Flash Device	Kyösti Mälkki
2012-07-03	AGESA F15 wrapper for Trinity	zbao
2012-07-02	Use broadcast SIPI to startup siblings	Sven Schnelle
2012-07-02	Intel CPUs: execute microcode update only once per core	Kyösti Mälkki
2012-05-30	Add support for Panther Point to SPI driver	Stefan Reinauer
2012-05-24	cbtypes.h: Unify cbtypes.h used in AMD board's code	Vikram Narayanan
2012-05-11	Hook up MRC cache update	Stefan Reinauer
2012-05-10	Add SPI flash driver	Stefan Reinauer
2012-05-08	Add config_enabled() from Linux	Patrick Georgi
2012-05-08	Clean up #ifs	Patrick Georgi
2012-05-01	Allow device ID arrays in the PCI driver structure	Vadim Bendebury
2012-04-27	SMM: unify mainboard APM command handlers	Stefan Reinauer
2012-04-27	cpu/cpu.h: add ROMCC guards	Stefan Reinauer
2012-04-27	Move top level pc80 directory to drivers/	Stefan Reinauer
2012-04-26	Revamp Intel microcode update code	Stefan Reinauer
2012-04-25	Replace cache control magic numbers with symbols	Patrick Georgi
2012-04-16	S3 code in coreboot public folder.	zbao
2012-04-12	Add support for aligned allocation	Ron Minnich
2012-04-06	Fixes and Sandybridge support for lapic cpu init	Stefan Reinauer
2012-04-06	Add constants for fast path resume copying	Stefan Reinauer
2012-04-05	Fill out ChromeOS specific coreboot table extensions	Stefan Reinauer
2012-04-04	Add support to run SMM handler in TSEG instead of ASEG	Stefan Reinauer
2012-04-03	Add support for Intel Turbo Boost feature	Stefan Reinauer
2012-04-03	smbios: add support for onboard devices extended information	Stefan Reinauer
2012-04-02	Add a helper function to determine the number of enabled CPUs	Stefan Reinauer
2012-04-02	Align: Make sure 1 is treated as unsigned long instead of int	Stefan Reinauer
2012-03-30	Make MTRR min hole alignment 64MB	Duncan Laurie
2012-03-30	Add more timestamps in coreboot.	Stefan Reinauer
2012-03-30	Add timestamps for selfboot and acpi wake	Duncan Laurie
2012-03-30	Add TPM support to coreboot	Stefan Reinauer
2012-03-30	Add an option to keep the ROM cached after romstage	Stefan Reinauer
2012-03-29	Add infrastructure for global data in the CAR phase of boot	Gabe Black
2012-03-29	Detect whether the OXPCIE card is really present while in the ROM stage.	Gabe Black
2012-03-29	Add support for enabling PCIe Common Clock and ASPM	Duncan Laurie
2012-03-29	Refactor publishing CBMEM addresses through coreboot table.	Vadim Bendebury
2012-03-29	Add timestamp table pointer to the coreboot table.	Vadim Bendebury