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2020-09-14src/{device,include}: Use PNP_IDX_EN instead of magic numberElyes HAOUAS
Change-Id: I68590605e261ecaace9f3cea28cfa6ec3b913a8a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14src/include: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14include/superio/hwm5_conf.h: Fix copy-pasted commentsAngel Pons
Comments say `port`, but the actual function signature uses `base`. Change-Id: I28a2f24a9701aec2fb990ca2f38e5f2794e15f0c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45226 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14soc/intel/common/cpu: Update COS mask calculation for NEM enhanced modeAamir Bohra
Update the COS mask calculation to accomodate the RW data as per SoC configuration. Currently only one way is allocated for RW data and configured for non-eviction. For earlier platform this served fine, and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a single way. Hence update the number of ways to be configured for non- eviction as per total LLC size. The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/ way size gives the number of ways that need to be configured for non- eviction, instead of harcoding it to 1. TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892) as COS mask selection register and hence needs to be progarmmed accordingly. Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33 of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before MSR write instead of eax(maps 31:0). This implementation corrects that as well. BUG=b:149273819 TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced CAR configuration. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-12include/console/uart: make index parameter unsignedFelix Held
The UART index is never negative, so make it unsigned and drop the checks for the index to be non-negative. Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-11device: Fix incompatible-pointer-types build errorSubrata Banik
The build error `incompatible-pointer-types` occurs while using `pci_dev_request_bus_master` as part of device ops Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I3b1ce85b8db1ddf9ac860415edbe64694b91b3d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45122 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08pci_ids: Add Alder Lake DTT PCI IDsSubrata Banik
Add PCI IDs for Intel's Dynamic Tuning Technology (DTT) for ADL. Also add NULL terminator at end of pci_device_ids. Change-Id: If25b1f562567a833683b0b8796bd1d6cac0bd490 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45140 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08pci_ids: Add Alder Lake IPU PCI IDsSubrata Banik
Add PCI IDs for Intel's Image Processing Unit (IPU) for ADL. Also add NULL terminator at end of pci_device_ids. Change-Id: I327828d676422fc6162fadffd9b39529ecb89ace Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08soc/intel/elkhartlake: Add CPU, SA, PCH & IGD DIDs TableTan, Lean Sheng
1. Add CPU, SA, PCH & IGD DIDs table into report_platform.c 2. Add additional EHL SA DID in pci_ids.h Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I5c98089873b17f82560eba13c7de3353b6d3e249 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08cpu/x86: Add definition for SMRR_PHYS_MASK_LOCKTim Wawrzynczak
The IA32_SMRR_PHYS_MASK MSR contains a 'Lock' bit, which will cause the core to generate a #GP if the SMRR_BASE or SMRR_MASK registers are written to after the Lock bit is set; this is helpful with securing SMM. BUG=b:164489598 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I784d1d1abec0a0fe0ee267118d084ac594a51647 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-07ec/system76: Add console supportJeremy Soller
This adds support for line-buffered console output to System76 EC firmware. Once the print command is received, the EC firmware multiplexes the output to any enabled console on the EC. This can be a memory ringbuffer, a parallel port (using the keyboard connector), or i2c (using the battery connector). Once the entire buffer is sent, it sets the command register to 0, indicating completion. For more information, please see: https://github.com/system76/ec/blob/master/doc/debugging.md Tested on system76/lemp9 with CONSOLE_SYSTEM76_EC enabled. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I861bf3e22f40dd6c3ec7ba1d73711b399358e332 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-03memory_info: add max_speed_mts and configured_speed_mtsRob Barnes
ddr_frequency is ambiguous and is interpreted differently in several places. Instead of renaming this field, this deprecates it and adds two new fields with unambiguous naming, max_speed_mts and configured_speed_mts. smbios.c falls back to using ddr_frequency when either of these fields are 0. The same value was being used for both configured memory speed and max memory speed in SMBIOS type 17, which is not accurate when configured speed is not the max speed. BUG=b:167218112 TEST=Boot ezkinil, no change to dmidecode -t17 Change-Id: Iaa75401f9fc33642dbdce6c69bd9b20f96d1cc25 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44549 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-01{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistentSubrata Banik
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-31device: Add method to configure bus mastering based on KconfigFelix Singer
The bus master bit is set at many places in coreboot's code, but the reason for that is not quite clear. We examined not setting the bus master bit whereever possible and tried booting without it, which worked fine for internal PCI devices but not for PCIe. As a PCIe device we used a Samsung M.2 NVMe SSD. For security reasons, we would like to disable bus mastering where possible. Depending on the device, bus mastering might get enabled by the operating system (e.g. for iGPU) and it might be required for some devices to work properly. However, the idea is to leave it disabled and configure the IOMMU first before enabling it. To have some sort of "backwards compatibility", add a method which configures bus mastering based on an additional config option. Since CB:42460 makes usage of this treewide, enable it by default to keep the current behaviour for now. Tested with Siemens/Chili, a Coffee Lake based platform. Change-Id: I876c48ea3fb4f9cf7b6a5c2dcaeda07ea36cbed3 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42459 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31include/device/azalia_device: Fix typoPatrick Rudolph
The code using the macro was found not working after finally enabling the HDA PCI device on the hermes board. Fix a typo to generate the correct verbs. Tested on prodrive/hermes. Change-Id: I953c2e9fbebc1f02bdf71ce868a95f578300c3a1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44900 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31fw_config: Add caching to successfully probed fieldsTim Wawrzynczak
Add a backing cache for all successfully probed fw_config fields that originated as `probe` statements in the devicetree. This allows recall of the `struct fw_config` which was probed. BUG=b:161963281 TEST=tested with follower patch Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0d014206a4ee6cc7592e12e704a7708652330eaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/44782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-31{intel/gma,include/device}: Delete unused 'drm_dp_helper.h' fileElyes HAOUAS
'drm_dp_helper.h' file is duplicated and not used. Change-Id: Ibb08f7ff91c3914940dfe899be331b06e292c7c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-29PCI IDs: Add PCI ID for CML DPTF/DTT PCI deviceEdward O'Callaghan
This PCI ID is required in order for the CML devices to perform SSDT generation for DPTF. CML Processor, EDS, Vol 1, Table 9-5, Section 9.2. BUG=b:158986928 BRANCH=puff TEST=builds Signed-off-by: Edward O'Callaghan <quasisec@google.com> Change-Id: I94aea6b9e0f60656827daada7b2cc2741604b8b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Andrew McRae <amcrae@google.com>
2020-08-27symbols: Change implementation details of DECLARE_OPTIONAL_REGION()Julius Werner
It seems that GCC's LTO doesn't like the way we implement DECLARE_OPTIONAL_REGION(). This patch changes it so that rather than having a normal DECLARE_REGION() in <symbols.h> and then an extra DECLARE_OPTIONAL_REGION() in the C file using it, you just say DECLARE_OPTIONAL_REGION() directly in <symbols.h> (in place and instead of the usual DECLARE_REGION()). This basically looks the same way in the resulting object file but somehow LTO seems to like it better. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I6096207b311d70c8e9956cd9406bec45be04a4a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-08-27soc/intel/common: Include Elkhart Lake SA IDsTan, Lean Sheng
Add additional Elkhart Lake specific SA IDs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I41af9b17b8121f3b47f2242d9beeec297893b378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40854 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-26include/imd: Improve API documentationJan Dabros
Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I8261c7d933435ba9f29fc3172cdfe8bcae5c1af9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-24mrc_cache: Add mrc_cache fetch functions to support non-x86 platformsShelley Chen
Create two new functions to fetch mrc_cache data (replacing mrc_cache_get_current): - mrc_cache_load_current: fetches the mrc_cache data and drops it into the given buffer. This is useful for ARM platforms where the mmap operation is very expensive. - mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a given buffer. This is useful for platforms where the mmap operation is a no-op (like x86 platforms). As the name mentions, we are not freeing the memory that we allocated with the mmap, so it is the caller's responsibility to do so. Additionally, we are replacing mrc_cache_latest with mrc_cache_get_latest_slot_info, which does not check the validity of the data when retrieving the current mrc_cache slot. This allows the caller some flexibility in deciding where they want the mrc_cache data stored (either in an mmaped region or at a given address). BUG=b:150502246 BRANCH=None TEST=Testing on a nami (x86) device: reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24soc/amd/picasso: Add console & timestamp buffers to psp_verstageMartin Roth
Create areas for console & timestamp data in psp_verstage and pass it to the x86 to save for use later. BUG=b:159220781 TEST=Build & Boot trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I41c8d7a1565e761187e941d7d6021805a9744d06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-21lib: Update fmap cache error for psp_verstageMartin Roth
The assumption was that the fmap cache would be initialized in bootblock, otherwise an error is shown. This error is showing up in psp_verstage when the fmap cache is initialized there, so create a new ENV value for ENV_INITIAL_STAGE. BUG=None TEST=Boot, see that error message is gone from psp_verstage Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I142f2092ade7b4327780d423d121728bfbdab247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43488 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21acpi: add more AML generation functionsAaron Durbin
Add the following functions to acpi AML generation code: acpigen_write_to_integer_from_namestring() acpigen_write_create_byte_field() acpigen_write_create_word_field() acpigen_write_create_dword_field() acpigen_write_create_qword_field() BUG=b:163583825 Change-Id: Ida151aff68f90012b16df2383fb96ddb87c3fb9c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44641 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21include/asan.h: Add missing includesElyes HAOUAS
<stdint.h> and <stddef.h> are missing. Change-Id: I10520013bb5ceb3aec0d24715f371f77e4300a70 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2020-08-21arch/x86: Add support for ASan to memory functionsHarshit Sharma
Compiler's instrumentation cannot insert asan memory checks in case of memory functions like memset, memcpy and memmove as they are written in assembly. So, we need to manually check the memory state before performing each of these operations to ensure that ASan is triggered in case of bad access. Change-Id: I2030437636c77aea7cccda8efe050df4b77c15c7 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-21lib: Add ASan support to romstage on x86 archHarshit Sharma
This patch adds ASan support to romstage on x86 architecture. A Kconfig option is added to enable ASan in romstage. Compiler flags are updated. A memory space representing the shadow region is reserved in linker section. And a function call to asan_init() is added to initialize shadow region when romstage loads. Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-21lib: Add ASan support to ramstage on x86 archHarshit Sharma
This patch adds address sanitizer module to the library and reserves a linker section representing the shadow region for ramstage. Also, it adds an instruction to initialize shadow region on x86 architecture when ramstage is loaded. Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-20soc/amd/acpi: Move ACPI IVRS generation to corebootJason Glenesk
Add code for IVRS generation to coreboot. Publish coreboot generated structure rather than IVRS generated by FSP binary. Reference Doc: 48882_IOMMU_3.05_PUB.pdf BUG=b:155307433 TEST=Boot trembyle to shell and extract and compare IVRS tables and make sure they cover the same devices. Change-Id: I693f4399766c71c3ad53539634c65ba59afd0fe1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-08-19arch/x86/boot: Jump to payload in protected modePatrick Rudolph
* On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode. * Add a helper function to jump to arbitrary code in protected mode, similar to the real mode call handler. * Doesn't affect existing x86_32 code. * Add a macro to cast pointer to uint32_t that dies if it would overflow on conversion Tested on QEMU Q35 using SeaBIOS as payload. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-18elog: add ELOG_WAKE_SOURCE_GPIOAaron Durbin
Provide a GPIO-based wake source event for log caputre. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iaa15178a392f40156d8d10e9aedfd5a1e758eedb Reviewed-on: https://review.coreboot.org/c/coreboot/+/44532 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPEAaron Durbin
The wake source macro for GPE events was using 'GPIO'. However, current usage is really all GPEs. Therefore, provide clarity in the naming in order to allow for proper GPIO wake events that are separate from the ACPI GPE block. BUG=b:159947207 Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-18cpu/x86/smm/smm_stub: Add x86_64 supportPatrick Rudolph
Enable long mode in SMM handler. x86_32 isn't affected by this change. * Enter long mode * Add 64bit entry to GDT * Use x86_64 SysV ABI calling conventions for C code entry * Change smm_module_params' cpu to size_t as 'push' is native integer * Drop to protected mode after c handler NOTE: This commit does NOT introduce a new security model. It uses the same page tables as the remaining firmware does. This can be a security risk if someone is able to manipulate the page tables stored in ROM at runtime. USE FOR TESTING ONLY! Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
2020-08-17soc/intel/common: Move common HDA registers to <device/azalia_device.h>Elyes HAOUAS
Change-Id: I9ea191e5076e2f055405dc34d46dbbb8cfb0015e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44106 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17lib/imd_cbmem.c: Add a helper function to indicate that cbmem is readyArthur Heymans
This can be used in romstage in particular to know if dram is ready. Change-Id: I0231ab9c0b78a69faa762e0a97378bf0b50eebaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dramArthur Heymans
INVD is called below so if postcar is running in a cached environment it needs to happen. NOTE: postcar cannot execute in a cached environment if clflush is not supported! Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17soc/intel/jasperlake: Add IGD Device IDKrishna Prasad Bhat
Add IGD Device ID for Jasperlake. Reference is taken from Jasperlake EDS volume 1(Document Number: 613601). TEST=Build and boot Jasperlake platform. Change-Id: Iab3ba286f36afbf9533ac3cc62891fa390ca2441 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44000 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-15cpu/x86/smm: Introduce SMM module loader version 2Rocky Phagura
Xeon-SP Skylake Scalable Processor can have 36 CPU threads (18 cores). Current coreboot SMM is unable to handle more than ~32 CPU threads. This patch introduces a version 2 of the SMM module loader which addresses this problem. Having two versions of the SMM module loader prevents any issues to current projects. Future Xeon-SP products will be using this version of the SMM loader. Subsequent patches will enable board specific functionality for Xeon-SP. The reason for moving to version 2 is the state save area begins to encroach upon the SMI handling code when more than 32 CPU threads are in the system. This can cause system hangs, reboots, etc. The second change is related to staggered entry points with simple near jumps. In the current loader, near jumps will not work because the CPU is jumping within the same code segment. In version 2, "far" address jumps are necessary therefore protected mode must be enabled first. The SMM layout and how the CPUs are staggered are documented in the code. By making the modifications above, this allows the smm module loader to expand easily as more CPU threads are added. TEST=build for Tiogapass platform under OCP mainboard. Enable the following in Kconfig. select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON_BLOCK_SMM select SMM_TSEG select HAVE_SMI_HANDLER select ACPI_INTEL_HARDWARE_SLEEP_VALUES Debug console will show all 36 cores relocated. Further tested by generating SMI's to port 0xb2 using XDP/ITP HW debugger and ensured all cores entering and exiting SMM properly. In addition, booted to Linux 5.4 kernel and observed no issues during mp init. Change-Id: I00a23a5f2a46110536c344254868390dbb71854c Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10soc/intel/common: Include Alder Lake SATA controller device IDsSubrata Banik
Document Number: 619501, 619362 Change-Id: Id3440b415ca80edebb6880b8b48f6094ebea4ae4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-05drivers/genesyslogic/gl9763e: Add driver for Genesys Logic GL9763EBen Chuang
The device is a PCIe to eMMC bridge controller to be used in the Chromebook as the boot disk. The datasheet name is GL9763E and the revision is 02. The patch sets single request AXI, disables ASPM L0s and enables SSC. Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Change-Id: I158c79f5ac6e559f335b6b50092469c7b1646c56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-05include/device/azalia_device.h: Include <stdint.h>Elyes HAOUAS
This file only needs <stdint.h>. So replace <types.h> with <stdint.h>. Change-Id: Ib58532837941d5324b28bc2c607d70555ce9caee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44134 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05soc/intel/common: Include Alder Lake device IDsSubrata Banik
Add Alder Lake specific CPU, System Agent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 619362 Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-04src/lib: Remove unused function parameters in imd.cAnna Karas
Remove const struct imd *imd and const struct imdr *imdr parameters from the prototypes of imdr_entry_size(), imd_entry_size() and imd_entry_id() functions since they are not used anywhere. Signed-off-by: Anna Karas <aka@semihalf.com> Change-Id: I6b43e9a5ae1f1d108024b4060a04c57f5d77fb55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43999 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03assert.h: Try to evaluate assertions at compile timeJulius Werner
Many places in coreboot seem to like to do things like assert(CONFIG(SOME_KCONFIG)); This is somewhat suboptimal since assert() is a runtime check, so you don't see that this fails until someone actually tries to boot it even though the compiler is totally aware of it already. We already have the dead_code() macro to do this better: if (CONFIG(SOME_KCONFIG)) dead_code(); Rather than fixing all these and trying to carefully educate people about which type of check is more appropriate in what situation, we can just employ the magic of __builtin_constant_p() to automatically make the former statement behave like the latter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I06691b732598eb2a847a17167a1cb92149710916 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-03lib/string: Add standard strstr() functionJes Klinke
Adding implementation of standard library strstr() See https://review.coreboot.org/c/coreboot/+/43741 for context. Change-Id: I63e26e98ed2dd15542f81c0a3a5e353bb93b7350 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-31mb/ocp/deltalake: Update SMBIOS type 4 -- Processor InformationMorgan Jang
TEST=Execute "dmidecode -t 4" to check if the processor information is correct for Deltalake platform Change-Id: I5d075bb297f2e71a2545ab6ad82304a825ed7d19 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-30smbios: Fix type 17 for Windows 10Patrick Rudolph
The `GetPhysicallyInstalledSystemMemory` API call, at least on Windows 10, returns an error if SMBIOS tables are invalid. Various tools use this API call and don't operate correctly if this fails. For example, the "Intel Processor Diagnostic Tool" program is affected. Windows then guesses the physical memory size by accumulating entries from the firmware-provided memory map, which results in a total memory size that is slightly lower than the actual installed memory capacity. To fix this issue, add the handle to a type 16 entry to all type 17 entries. Add new fields to struct memory_info and fill them in Intel common code. Use the introduced variables to fill type 16 in smbios.c and provide a handle to type 17 entries. Besides keeping the current behaviour on intel/soc/common platforms, the type 16 table is also emitted on platforms that don't explicitly fill it, by using the existing fields of struct memory_info. Tested on Windows 10: The GetPhysicallyInstalledSystemMemory API call doesn't return an error anymore and the installed memory is now being reported as 8192 MiB. Change-Id: Idc3a363cbc3d0654dafd4176c4f4af9005210f42 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-28device: Add find_dev_nested_path helper functionRob Barnes
Add find_dev_nested_path helper function to simplify finding deeply nested devices. BUG=b:157580724 TEST=Find bluetooth device on dalboz Change-Id: I48fa5fcad0030fb6dcea97b9fc76e1d3d3f9b28f Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-28arch/x86/smbios: Bump to version 3.0Patrick Rudolph
Fill in the new fields introduced with version 3.0 and install the new entry point structure identified by _SM3_. Tested on Linux 5.6 using tianocore as payload: Still able to decode the tables without errors. Change-Id: Iba7a54e9de0b315f8072e6fd2880582355132a81 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 03:50:24 +0000