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2009-04-30Remove warnings from compilation of the s2892 with and without CBFS.Myles Watson
I didn't try to remove "defined but not used" warnings because there are too many ifdefs to be sure I wouldn't break something. For shadowed variable declarations I renamed the inner-most variable. The one in src/pc80/keyboard.c might need help. I didn't change the functionality but it looks like a bug. I boot tested it on s2892 and abuild tested it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22This patch adds support for the BCM21000 (aka HT-2100)Mondrian nuessle
PCIe bridge. Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de> Acked-by: Samuel Verstraete <samuel.verstraete@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4182 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22* Allow coreboot to use the full 256 bytes of CMOS memoryStefan Reinauer
* Make functions out of the accessor macros in mc146818rtc.c * don't hide reserved cmos entries from coreboot, only from the user. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21- function prototypes do not need "extern"Stefan Reinauer
- fix up debug messages of usb debug console (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21add define for Role-Based Error Reporting to PCIe defines (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21Eliminate various issues brought up by scan-build.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-17Add VIA CX700 support, plus VIA vt8454c reference board support.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-17This needed to be removed. Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14v2/src romfs->cbfs renamePeter Stuge
This also has the config tool changes in v2/util. Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-10unify spd_ddr2.h (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-06(trivial) fix some warningsStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03These are some cleanups and changes. These are build and boot tested on qemu.Ronald G. Minnich
Some changes for option roms: - don't make users pick the name. Names for option roms are in the v3-defined format of pci%04x,%04x.rom with the vendor and device id filling in the %04x. - users pass in vendor and device id. - users pass in a dest. If the dest is 0, the address of the ROM image in FLASH is returned. If the address is non-zero, then the decmpressor is called, and it will make sure the ROM image is copied to the destination (even in the uncompressed case). And some type and print cleanup. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01forgot this. Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01Drop CONFIG_CHIP_NAME. Those config statements in Config.lb shouldStefan Reinauer
be used unconditionally, and the names don't hurt. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17This patch adds "high coreboot table support" to coreboot version 2.Stefan Reinauer
Some bootloaders seem to overwrite memory starting at 0x600, thus destroying the coreboot table integrity, rendering the table useless. By moving the table to the high tables area (if it's activated), this problem is fixed. In order to move the table, a 40 bytes mini coreboot table with a single sub table is placed at 0x500/0x530 that points to the real coreboot table. This is comparable to the ACPI RSDT or the MP floating table. This patch also adds "table forward" support to flashrom and nvramtool. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-15Fix all build problems on PPC except the _SDA_BASE issues caused by theStefan Reinauer
code expecting too old binutils(?). Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13This, ladies and gentlement, is commit #4000.Stefan Reinauer
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few include files and missing prototypes. Also, fix up the Config-abuild.lb files to properly work for cross compiling. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06* fix a minor power state issue in the ich7 smm handlerStefan Reinauer
* move mainboard dependent code into a mainboard SMI handler. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06Fix mmconf (PCIe memory mapped config space access) support in v2. It wasStefan Reinauer
horribly broken and thus never used by any platform. This needs to get straightened out so current chipsets drivers can use the full feature set. Create wrapper functions similar to the io pci config space ones. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-01Some changes required to get yabel working on v2 (and they generally makeStefan Reinauer
sense, too). Have one u64 instead of three. In order to use the old bios emulator, you have to do nothing. (Default, if CONFIG_PCI_ROM_RUN is enabled) In order to use yabel in your target, you need to add the following lines to your config: uses CONFIG_PCI_OPTION_ROM_RUN_YABEL default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1 In order to use vm86 in your target, you need to add the following lines to your config: uses CONFIG_PCI_OPTION_ROM_RUN_VM86 default CONFIG_PCI_OPTION_ROM_RUN_VM86=1 Note: vm86 only works on platforms with _RAMBASE in the lower megabyte. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3Stefan Reinauer
a long time ago. This will make it easier to port v2 boards forward to v3 at some point (and other things) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-27Generic approach of putting BIOS tables at the end of memoryStefan Reinauer
(in addition to their low locations) This adds the kontron 986LCD-M and the i945 as a sample. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-14Change Log:Rudolf Marek
Bellongs to r3947 Following patch adds dynamically generated P-States infrastructure as well as M2V-MX SE as example how to do that. It is based on AMD code and mine code for ACPI generation. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20add a header file for i8259.h (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20Backport all x86emu fixes from Pattrick Hueper to coreboot v2 (acked in v2,Stefan Reinauer
hence I consider it trivial in this case). This does not include the Yabel work. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20fix compiler warnings (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20Check the printk format string against the matching arguments. We haveCarl-Daniel Hailfinger
this type of checking in the v3 code since ages, but v2 will happily compile any code with bogus printk format strings and/or parameters. This can cause real bugs and at least needs to emit a warning, if not an error. Go with a warning for now since most of the flagged format strings are wrong but harmless in a 32-bit x86 environment. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23The attached patch adds missing bits to ACPI to make Windows XP and Windows ↵Rudolf Marek
Vista happy. The FADT bootarch flags Blacklists MSI for this chipset (maybe not needed) Adds modified amdk8_util.asl Adds the SSDT table to chain of tables Aligns the FACS correctly (this should be done for other boards) Adds the _CRS method to Asus M2V-MX SE acpi DSDT. Fixes the FACS table length. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19Fix a LOT of implicit function declarations before they become errors.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18This patch gets rid of all the implicit definition warnings for serengeti ↵Myles Watson
except get_nodes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-13Move mainboard specific changes to the coreboot memory table into theStefan Reinauer
mainboard specific code. (And add a hook to allow other mainboards do a similar thing if required) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11[PATCH] coreboot-v2: Add multiboot supportRobert Millan
Signed-off-by: Robert Millan <rmh@aybabtu.com> Acked-by: Jordan Crouse <jordan@cosmicpneguin.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31Revert i945/ICH7 PCI IDs to be hard-coded numbers instead of #defines.Uwe Hermann
Build-tested on kontron_986lcd_m. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29i945/ICH7: Use #defines from pci_ids.h (trivial).Uwe Hermann
Build-tested with the kontron/986lcd-m target. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for the Intel ICH7 southbridge.Stefan Reinauer
This includes an early SMI handler. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-13Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.Uwe Hermann
Build-tested with the AMD dbm690t board. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22Patch for AMD RS690 chipset.Michael Xie
All the PCIe slots are enabled in this patch except power management. Signed-off-by: Michael Xie <Michael.Xie@amd.com> Reviewed-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-05This patch adds support for the VIA VT8237S south bridge. The VT8237R ↵Rudolf Marek
programming remains unchanged (tested on mine desktop) except of reverting the small change introduced by Bari (gpio/inta setup reg 0x5b). This should go for some board specific file. The change would broke at least mine board. But seems to be needed for jakllsch. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Bari Ari <bari@onelabs.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28Add definitions for DDR2 SPD registers.Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25This patch adds PCI device IDs for the Intel EP80579 Integrated Processor,Ed Swierk
and renames some existing macros for clarity. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02Go back to SIPI WAIT state for those CPUS defining the newly introducedStefan Reinauer
CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with multiple cores. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01add some SPD values from specs. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01function prototypes don't need extern. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-29Adds a field to the serial port descriptor about the configured line speed.Patrick Georgi
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20Following patch adds K8M890 support. It initializes the AGP and graphics UMA.Rudolf Marek
The V-link setup and HT bridge is redone, because VT8237A has it in another device. So far following combination of chipsets should now work: K8T890CE + VT8237R K8M890(CE) + VT8237R VIA PC1 brige moved to NB code (vt8237r_bridge.c -> k8t890_bridge.c) and notes about K8M890 support were added. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-19Following patch will setup KT890 HT automatically. It will find theRudolf Marek
max width of the link and also it will take the frequency of K8 HT already done coreboot (and checks if t can run on it). Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16oops. sorry, wrong checkin. This patch backs out r3155 and instead contains theEd Swierk
code it should have contained. This patch updates the PCI IDs for Intel 3100 devices. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-21Add support for the Via CN700 with a C7 CPU and DDR2 RAM. Only a single DIMM isCorey Osgood
working for now, and more work is needed for it to be fully dynamic. However, just about any 128MB-512MB DIMM should work. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-01 This patch fixes the decoding of the IO address range 0x0820->0x0827 into theFlorentin Demetrescu
LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI interface of the IT8716 SIO chip. Changes : 1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some functions of a PNP device can have more than 12 resources (ex the GPIO function of IT8716f), in which case one could have an "array overflow" inside the device structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at device init time..) 2) - define resource masks for the GPIO function in src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO ranges which are set into the LPC bridge of the SB are very strange (f.ex.: 0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching by the init code 3) - enable the flash SPI interface into src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource into the GPIO function). I know that this is problematic because not all m57sli boards are SPI, but .. do anyone have a better idea how to handle this?.. Signed-off-by: Florentin Demetrescu <echelon@free.fr> I (Ward) have verified your patch on a rev2 of this board (it works!) as well as on a rev1 (plcc). It does not affect flashing on rev1 nor have any averse side effects that I noticed, so I think this patch should go in. Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27Add a new record type "console" for lbtable, and insert one recordPatrick Georgi
for each output device we support, so the payload can figure out where to find consoles that the user cares about. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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