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2020-07-04smbios: TYPE_NONE and TYPE_OTHER are already takenPatrick Georgi
Change-Id: Ic66f7c919a71cb53773d5056e5f756cd6faf4909 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43135 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04post_code: reorganize order of postcode definesSindhoor Tilak
Currently, the certain postcode values aren't in increasing order of values. The change, just reorganzies the defines in increasing order of the values Signed-off-by: Sindhoor Tilak <sindhoor@sin9yt.net> Change-Id: Id5f0ddc4593f689829ab9a7fdeebd5f66939bf79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04arch/x86/smbios: Add SMBIOS type8 dataBryantOu
Refer to section 7.9 Port Connector Information of DSP0134_3.3.0 to add type 8 data, the table of data should be ported according to platform design and MB silkscreen. Change-Id: I81e25d27c9c6717750edf1d547e5f4cfb8f1da14 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-02acpi_device: Replace polarity with active_low in acpi_gpio for GpioIoFurquan Shaikh
As per ACPI spec, GpioIo does not have any polarity associated with it. Linux kernel uses `active_low` argument within GPIO _DSD property to allow BIOS to indicate if the corresponding GPIO should be treated as active low. Thus, if GPIO has active high polarity or if it does not have any polarity associated with it, then the `active_low` argument is supposed to be set to 0. Having a `polarity` field in acpi_gpio seems confusing because GPIOs might not always have polarity associated with them. Example, in case of DMIC-select GPIO where 0 means select DMIC0 and 1 means select DMIC1, there is no polarity associated with the GPIO. Thus, it would be clearer for mainboard to use macros without having to specify a particular polarity. In order to enable mainboards to provide GPIO information without polarity for GpioIo usage, this change also adds `ACPI_GPIO_OUTPUT` and `ACPI_GPIO_INPUT` macros. BUG=b:157603026 Change-Id: I39d2a6ac8f149a74afeb915812fece86c9b9ad93 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02acpi_device: Add helper macros for setting acpi_gpio fieldsFurquan Shaikh
This change adds helper macros for initializing acpi_gpio fields for GpioIo/GpioInt objects. This allows dropping some redundant code for each macro to set the structure fields. Change-Id: Id0a655468759ed3035c6c1e8770e37f1275e344e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01ACPI GNVS: Replace uses of smm_get_gnvs()Kyösti Mälkki
Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25arch/x86/smbios: Add more fields to be overriden for type 3 and 4Johnny Lin
For type 3, override chassis asset_tag_number with smbios_mainboard_asset_tag() and add two functions that can override chassis version and serial_number. For type 4 add smbios_processor_serial_number() to override serial_number. Tested on OCP Tioga Pass. Change-Id: I80c6244580a4428fab781d760071c51c7933abee Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-24ACPI: Replace smm_setup_structures()Kyösti Mälkki
Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-24ACPI: Add framework for GNVS initialisationKyösti Mälkki
Provide common initialisation point for setting up GNVS structure before first SMI is triggered. Change-Id: Iccad533c3824d70f6cbae52cc8dd79f142ece944 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42423 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22device/smbus_host: Declare common early SMBus prototypesKyösti Mälkki
Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22cpu/x86/lapic: Support x86_64 and clean up codePatrick Rudolph
Most LAPIC registers are 32bit, and thus the use of long is valid on x86_32, however it doesn't work on x86_64. * Don't use long as it is 64bit on x86_64, which breaks interrupts in QEMU and thus SeaBIOS wouldn't time out the boot menu * Get rid of unused defines * Get rid of unused atomic xchg code Tested on QEMU Q35 with x86_64 enabled: Interrupts work again. Tested on QEMU Q35 with x86_32 enabled: Interrupts are still working. Tested on Lenovo T410 with x86_64 enabled. Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36777 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22soc/amd/picasso/bootblock: Write EIP to secure S3Raul E Rangel
This change is required so we have a defined entry point on S3. Without this, the S3_RESUME_EIP_MSR register could in theory be written to later which would be a security risk. BUG=b:147042464 TEST=Resume trembyle and see bootblock start. coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 smm starting (log level: 8)... SMI# #6 SMI#: SLP = 0x0c01 Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) PSP: Prepare to enter sleep state 3... OK SMU: Put system into S3/S4/S5 Timestamp - start of bootblock: 18446744070740509170 coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 bootblock starting (log level: 8)... Family_Model: 00810f81 PMxC0 STATUS: 0x200800 SleepReset BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) Timestamp - end of bootblock: 18446744070804450274 VBOOT: Loading verstage. FMAP: area COREBOOT found @ c75000 (3715072 bytes) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 61b80 size cee4 PROG_RUN: Setting MTRR to cache stage. base: 0x04000000, size: 0x00010000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b0b0d0d576fc42b1628a4547a5c9a10bcbe9d37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-22cpu/x86/smm: Define APM_CNT_ROUTE_ALL_XHCIKyösti Mälkki
Change-Id: I0bc321f499278e0cdbfb40be9a2b2ae21828d2f4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22cpu/x86/smm: Define APM_CNT_NOOP_SMIKyösti Mälkki
Old (!PARALLEL_MP) cpu bringup uses this as the first control to do SMM relocation. Change-Id: I4241120b00fac77f0491d37f05ba17763db1254e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-18ACPI: Clean up some S3 related leftoversKyösti Mälkki
With RELOCATABLE_RAMSTAGE the backing up of low memory on S3 resume path was dropped. We forgot some things behind. Change-Id: I674f23dade0095e64619af0ae81e23368b1ee471 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-17treewide: Replace CONFIG(ARCH_xx) testsKyösti Mälkki
Once we support building stages for different architectures, such CONFIG(ARCH_xx) tests do not evaluate correctly anymore. Change-Id: I599995b3ed5c4dfd578c87067fe8bfc8c75b9d43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17device/pnp_ops.h: Use pnp.h functionsAngel Pons
With BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3ca080e700cf7b7f5b76cadddc7e41960413433c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42133 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17cpu/x86/smm: Add helper functions to verify SMM accessPatrick Rudolph
* Add a function to check if a region overlaps with SMM. * Add a function to check if a pointer points to SMM. * Document functions in Documentation/security/smm To be used to verify data accesses in SMM. Change-Id: Ia525d2bc685377f50ecf3bdcf337a4c885488213 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41084 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16cpu/x86: Define MTRR_CAP_PRMRRKyösti Mälkki
Followups will remove remaining cases of PRMRR_SUPPORTED and SMRR_SUPPORTED in the tree. Change-Id: I7f8c7d98f5e83a45cc0787c245cdcaf8fab176d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16sb,soc/intel: Replace smm_southbridge_enable_smi()Kyösti Mälkki
Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)Kyösti Mälkki
Change-Id: I8c4dc5ab91891de9737189bd7ae86df18d86f758 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16arch/x86: Declare global_smi_enable()Kyösti Mälkki
The call made at mp_ops.post_mp_init() generally uses four different names. Unify these with followups. smm_southbridge_enable(SMI_EVENTS) smm_southbridge_enable_smi() hudson_enable_smi_generation() enable_smi_generation() Furthermore, some platforms do not enable power button SMI early. It may be preferred to delay the enablement, but fow now provide global_smi_enable_no_pwrbtn() too. Change-Id: I6a28883ff9c563289b0e8199cd2ceb9acd6bacda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-16arch/x86: Create helper for APM_CNT SMI triggersKyösti Mälkki
Attempts to write to APM_CNT IO port should always be guarded with a test to verify SMI handler has been installed. Immediate followup removes redundant HAVE_SMI_HANDLER tests. Change-Id: If3fb0f1a8b32076f1d9f3fea9f817dd4b093ad98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41971 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15include: update cbmem_possibly_online for vboot_before_bootblockMartin Roth
cbmem is not online when vboot runs before the bootblock. Update the macro to reflect that. BUG=b:158124527 TEST=Build & boot psp_verstage on trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I6fb4ad04f276f2358ab9d4d210fdc7a34a93a5bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/42066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-15include/rules.h: Add vboot_before_bootblock to ENV_ROMSTAGE_OR_BEFOREMartin Roth
BUG=b:158124527 TEST=Build & boot Trembyle with PSP verstage Change-Id: I3f5cc4d396c678f1020409cbdcb5127b2e0e6d89 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42379 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15arch/x86: Remove XIP_ROM_SIZEKyösti Mälkki
When adding XIP stages on x86, the -P parameter was used to pass a page size that covers the entire file to add. The same can now be achieved with --pow2page and we no longer need to define a static Konfig for the purpose. TEST: Build asus/p2b and lenovo/x60 with "--pow2page -v -v" and inspect the generated make.log files. The effective pagesize is reduced from 64kB to 16kB for asus/p2b giving more freedom for the stage placement inside CBFS. Pagesize remained at 64kB for lenovo/x60. Change-Id: I5891fa2c2bb2d44077f745619162b143d083a6d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-14drivers/intel/fsp2_0: Add FSP 2.2 specific supportSubrata Banik
• Based on FSP EAS v2.1 – Backward compatibility is retained. • Add multi-phase silicon initialization to increase the modularity of the FspSiliconInit() API. • Add FspMultiPhaseSiInit() API • FSP_INFO_HEADER changes o Added FspMultiPhaseSiInitEntryOffset • Add FSPS_ARCH_UPD o Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. FSP 2.2 Specification: https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41728 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10device/xhci: Add xHCI utility to enumerate capabilitiesRaul E Rangel
This will allow enumerating an xHCI controller to allow dynamically generating the ACPI device nodes. BUG=b:154756391 TEST=Boot trembyle and see capabilities printed on console xHCI Supported Protocol: Major: 0x2, Minor: 0x0, Protocol: 'USB ' Port Offset: 1, Port Count: 2 xHCI Supported Protocol: Major: 0x3, Minor: 0x10, Protocol: 'USB ' Port Offset: 3, Port Count: 1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3065c3fffad01b5378a55cfe904f971079b13d0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-10amd/00730F01: Clean the Microcode updatingZheng Bao
According to the comments of https://review.coreboot.org/c/coreboot/+/41719 , which is about Microcode patch for amd/picasso. Change the code with the same way. The changes include: 1. combine the microcode_xxx.c and update_microcode.c into one source. 2. Redefine the microcode updating function to eliminate the parameter. Get the revision ID in the black box. Reduce the depth of function calls. 3. Get the revision ID by bitwise calculation instead of lookup table. 4. Reduce the confusing type casts. 5. Squash some lines. We do not change the way it used to be. The code assume only one microcode is integrated in CBFS. If needed in future, 41719 is the example of integrating multiple binaries. And, 41719 depends on the definition in this patch. Change-Id: I8b0da99db0d3189058f75e199f05492c4e6c5881 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-10amd/common: Add the macro definition for patch level MSRZheng Bao
This MSR is used for detecting if the micro code is applied successfully. Change-Id: I060eb1a31f3358341ac0d5b9105e710c351f2ce8 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42212 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09pci_ops.h: Turn and/or ops into update wrappersAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I2d3779967f357dd380928869c630a1996fdd60ec Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-09include/device/pci_ops.h: Add bitwise AND opsAngel Pons
For the sake of completeness, we should provide these operations. Change-Id: Ia28af94ec86319c7380d8377f7e24e5cdf55dd9c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42145 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08spi: Remove non_volatile flag from block protection interfaceDaniel Gröber
Only Winbond parts seem to support making status register writes volatile. So this flag should not be exposed in the generic interface. Change-Id: Idadb65ffaff0dd7809b18c53086a466122b37c12 Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41746 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08device: Add a disabling PCIe device bus master functionJohn Zhao
A function pci_dev_disable_bus_master() is created. This function can be used to disable Thunderbolt PCIe root ports, bridges and devices for Vt-d based security platform at end of boot service. BUG=None TEST=Verified PCIe device bus master enable bit is cleared. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ie92a15bf2c66fdc311098acb81019d4fb7f68313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-07acpi: Rename motherboard_fill_fadt() to mainboard_fill_fadt()Kyösti Mälkki
The prefix mainboard_ was used everywhere else. Change-Id: Ie576fd47301aa484cb1396e0c6f7260b7698af4d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-07acpi,soc/intel: Make soc/motherboard_fill_fadt() globalKyösti Mälkki
Change-Id: Iad7e7af802212d5445aed8bb08a55fd6c044d5bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41916 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06drivers/pc80/rtc: Drop ARCH_X86 guard in headerKyösti Mälkki
Change-Id: I03c25ad5d9864406e1a021e39a5736ac72c8825a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38197 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06arch/x86: Declare permanent_smi_handler()Kyösti Mälkki
Advertising SMI triggers in FADT is only valid if we exit with SMI installed. There has been some experiments to delay SMM installation to OS, yet there are new platforms that allow some configuration access only to be done inside SMM. Splitting static HAVE_SMI_HANDLER variable helps to manage cases where SMM might be both installed and cleared prior to entering payload. Change-Id: Iad92c4a180524e15199633693446a087787ad3a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-04acpi: Add support for writing UART device descriptorsDuncan Laurie
This change adds support for generating the device descriptor that corresponds to the UARTSerialBusV2() ACPI macro. The resulting ACPI code for ACPI_UART_RAW_DEVICE(115200, 64) is: UartSerialBusV2 (0x0001C200, DataBitsEight, StopBitsOne, 0x00, LittleEndian, ParityTypeNone, FlowControlNone, 0x0040, 0x0040, "\\_SB.PCI0.UAR2", 0x00, ResourceConsumer, , Exclusive) Change-Id: I671ce2a499d74717d8677528c46ab3fbc1d7faf5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-04acpi: Accomodate non-standard UUIDs in device propertiesDuncan Laurie
There have been changes to the way device properties are supported in Linux[1] and Windows[2] which add flexibilty: - non-standard UUIDs can be used instead of only ACPI_DP_UUID - support for multiple different packages within the _DSD that associate different properties with unique UUIDs. To handle this I extracted the part that does the write of UUID and properties to a separate function and defined a new PACKAGE type which has the custom UUID as a name and can be used the same way that child properties are today. For example a PCIe root port for a USB4 port has a standard property indicating the USB4 reference, and then two custom properties which are defined for different attributes. Example code: /* Create property table */ acpi_dp *dsd = acpi_dp_new_table("_DSD"); acpi_dp_add_reference(dsd, "usb4-port", usb4_path); /* Add package for hotplug */ acpi_dp *pkg = acpi_dp_new_table("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"); acpi_dp_add_integer(pkg, "HotPlugSupportInD3", 1); acpi_dp_add_package(dsd, pkg); /* Add package for external port info */ pkg = acpi_dp_new_table("efcc06cc-73ac-4bc3-bff0-76143807c389"); acpi_dp_add_integer(pkg, "ExternalFacingPort", 1); acpi_dp_add_package(dsd, pkg); /* Write all properties */ acpi_dp_write(dsd); Resulting ACPI: Scope (\_SB.PCI0.TRP0) { Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package () { Package () { "usb4-port", \_SB.PCI0.TDM0.RHUB.PRTA } }, ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"), Package () { Package () { "HotPlugSupportInD3", One } }, ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"), Package () { Package () { "ExternalFacingPort", One }, } }) } [1] https://patchwork.kernel.org/patch/10599675/ [2] https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports Change-Id: I75f47825bf4ffc5e9e92af2c45790d1b5945576e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-03acpi: Drop typoed __ROMC__Kyösti Mälkki
Change-Id: I4fcec5bbc038a31565882631052ab07e38946e65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-03acpigen: Add some new helper functionsDuncan Laurie
These build on existing functions but use different object types in order to provide functions for upcoming changes: acpigen_write_return_op(): Return an operator. acpigen_write_if_lequal_op_op(): Check if 2 operands are equal. acpigen_get_package_op_element(): Read an element from a package into an operator. This one just provides the missing helper, the other 3 already exist: acpigen_get_tx_gpio: Read TX gpio state. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I1141fd132d6f09cf482f74e95308947cba2c5846 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41985 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02amd/microcode: Change equivalant ID width to 16bitZheng Bao
The definition of processor_rev_id in struct microcode is 16 bits. So we need to change the a series of parameters passing to 16 bits. Change-Id: Iacabee7e571bd37f3aca106d515d755969daf8f3 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-02fw_config: Add firmware configuration interfaceDuncan Laurie
This change introduces a new top-level interface for interacting with a bitmask providing firmware configuration information. This is motivated by Chromebook mainboards that need to support multiple different configurations at runtime with the same BIOS. In these devices the Embedded Controller provides a bitmask that can be broken down into different fields and each field can then be broken down into different options. The firmware configuration value could also be stored in CBFS and this interface will look in CBFS first to allow the Embedded Controller value to be overridden. The firmware configuration interface is intended to easily integrate into devicetree.cb and lead to less code duplication for new mainboards that make use of this feature. BUG=b:147462631 TEST=this provides a new interface that is tested in subsequent commits Change-Id: I1e889c235a81545e2ec0e3a34dfa750ac828a330 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02cpu/x86/mtrr: add x86_setup_mtrrs_with_detect_no_above_4gb()Aaron Durbin
There's not a function that is the equivalent to x86_setup_mtrrs_with_detect() but not solving for above 4GiB. Provide x86_setup_mtrrs_with_detect_no_above_4gb() which is the equivalent to x86_setup_mtrrs_with_detect() but instructs the MTRR solver to not take into account memory above 4GiB. BUG=b:155426691 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia1b5d67d6f139aaa929e03ddbc394d57dfb949e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41897 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02cpu/x86/mtrr: add helper for setting multiple MTRRsAaron Durbin
Introduce concept of var_mtrr_context object for tracking and assigning MTRR values. The algorithm is lifted from postcar_loader code, but it's generalized for different type of users: setting MSRs explicitly or deferring to a particular caller's desired actions. BUG=b:155426691,b:155322763 Change-Id: Ic03b4b617196f04071093bbba4cf28d23fa482d8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02src: Remove redundant includesElyes HAOUAS
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>, <stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes each time when <types.h> is included. Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-02cpu/x86/mtrr.h: Get rid of commonlib/helpers.h dependencyNico Huber
We want to use the CACHE_ROM_* macros in linker scripts. Avoid `commonlib/helpers.h` as it contains an ALIGN() macro definition that conflicts with the ALIGN keyword in linker scripts. Change-Id: I3bf20733418ca4135f364a3f6489e74d45e4f466 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41785 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02acpi: Add definitions for device sleep statesDuncan Laurie
The ACPI device sleep states are different from system sleep states and many places hardcode to specific values that are difficult to decode without referring to the spec. Change-Id: If5e732725b775742fd2a9fd0df697e312aa7bf20 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41791 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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