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2020-07-20src: Make HAVE_CF9_RESET set the FADT reset registerAngel Pons
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as reset register in FADT. How unsurprising. We might as well use that information to automatically fill in the FADT accordingly. So, do it. To avoid having x86-specific code under arch-agnostic `acpi/`, create a new optional `arch_fill_fadt` function, and override it for x86 systems. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-18dptf: Fix scope of TCPU deviceTim Wawrzynczak
In the initial DPTF refactor, the scope of the TCPU device was incorrectly set as \_SB, instead of \_SB.PCI0. However, because of the way that the acpi_inject_dsdt() callback currently works (it injects contents before the dsdt.aml file), the Scope where the TCPU device lives (\_SB.PCI0) doesn't exist yet. Therefore, to avoid playing games with *when* things are defined in the DSDT, switch to defining all of the DPTF devices in the SSDT. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia4922b4dc6544d79d44d39e6ad18c6ab9fee0fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43529 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17device: Increase DEVICE_PATH_MAX to 40Furquan Shaikh
This change increases the maximum length of device path string to 40 characters to accommodate growing hierarchy of devices. TEST=Ensured that "\_SB.PCI0.LPCB.EC0.CREC.TUN0.RT58" is correctly added to SSDT. Change-Id: Id2ef71a32b26e366b56c652942a247de4889544a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-15PCI IDs: Add PCI ID for JSL DPTF/DTT PCI deviceTim Wawrzynczak
This PCI ID is required in order for JSL devices to perform SSDT generation for DPTF. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I42209d15bc4f1654814465ce1412576f7349dddc Reviewed-on: https://review.coreboot.org/c/coreboot/+/43421 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12soc/intel/tigerlake: Add new IGD deviceRavi Sarawadi
Add new IGD device ID for new Tigerlake SKU support. BUG=b:160394260 Branch=None TEST=build, boot and check IGD device is reported. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I1903d513b61655d0e939f80b0fd0108091fdd7e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-12device/xhci: Add helper method to iterate over xhci_supported_protoclRaul E Rangel
There is some boilerplate required to iterate over the USB supported protocol structs. Encapsulate all the in a method to make the callers simpler. BUG=b:154756391 TEST=Built test trembyle. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I401f10d242638b0000ba697573856d765333dca0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43352 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11arch/x86: Drop CBMEM_TOP_BACKUPKyösti Mälkki
Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10include/acpi/acpi.h: Add ACPI_NAME_BUFFER_SIZERaul E Rangel
ACPI names can only be 4 characters long. Define a constant that defines the size of the name + the NUL terminator. BUG=b:154756391 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iad230c029f324005620ddad66c433ada26be78cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/43329 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09include/console/usb.h: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I216f8459afc69ced98ea1859ee6b1f8e4d43bc4a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definitionFelix Held
The SMM_LOCK bit isn't in SMM_MASK_MSR, but in HWCR_MSR, so move it there. The soc/amd/* code itself uses the bit definition when accessing HWCR_MSR, so SMM_LOCK was just below the wrong MSR definition. Also remove SMM_LOCK from comment about masking bits in SMM_MASK_MSR, since that bit isn't in that MSR. TEST=Checked the code and the corresponding BKDG/PPR. Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43309 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08ACPI: Add and fill gnvs_ptr for smm_runtimeKyösti Mälkki
Change-Id: I823d04a4851437b4267a60886e5ab205bb2e1b10 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-07acpigen: Add acpigen_notifyTim Wawrzynczak
A fairly common thing in ACPI is notifying a device when some kind of device-specific event happens; this function simplifies writing this pattern. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0f18db9cc836ec9249604452f03ed9b4c6478827 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42102 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07soc/intel/common/block: Add new block DTTTim Wawrzynczak
Intel Dynamic Tuning Technology is the name of a PCI device on some Intel SoCs. This minimal PCI driver is only used now for SSDT generation on TGL devices. Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41893 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07src/include: improve the description of hexstrtobinAnna Karas
Specify how hexstrtobin.c processes the strings of odd length. Signed-off-by: Anna Karas <aka@semihalf.com> Change-Id: Ie8cd8fb93d7dab08c5e7f28fc511b6381f5ad13a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43089 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07dptf: Add support for IDSPTim Wawrzynczak
\_SB.DPTF.IDSP adverties to the DPTF daemon which policies the implementation supports. Added a new acpigen function to figure out which policies are used, and fills out IDSP appropriately. Change-Id: Idf67a23bf38de4481c02f98ffb27afb8ca2d1b7b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Fan and TSR optionsTim Wawrzynczak
DPTF has several options on how to control the fan (fine-grained speed control, minimum speed change in percentage points, and whether or not the DPTF device should notify the Fan if it detects low speed). Individual TSRs can also set GTSH, which is the amount of hysteresis inherent in the measurement, either from circuitry (if analog), or in firmware (if digital). BUG=b:143539650 TEST=compiles Change-Id: I42d789d877da28c163e394d7de5fb1ff339264eb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Running Average Power LimitsTim Wawrzynczak
This change adds support for emitting the PPCC table, which describes the ranges available as knobs for DPTF to tune. It can support min/max power, min/max time window for averaging, and the minimum adjustment size (granularity or step size) of each power limit. The current implementation only supports PL1 and PL2. BUG=b:143539650 TEST=compiles Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Fan Performance StatesTim Wawrzynczak
This change adds support for generating the _FPS table for the DPTF Fan object. The table describes different levels of fan activity that may be applied to the system in order to actively cool it. The information includes fan speed at a (rough) percentage level, fan speed in RPM, potential noise level in centibels, and power in mA. BUG=b:143539650 TEST=compiles Change-Id: I5591eb527f496d0c4c613352d2a87625d47d9273 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Charger Performance StatesTim Wawrzynczak
This change generates the DPTF TCHG.PPSS table in the SSDT. This table describes different charging rates which are available to use. DPTF can pick different rates in order to passively cool (or not) the system. BUG=b:143539650 TEST=compiles Change-Id: I6df6bfbac628fa4e4d313e38b8e6c53fce70a7f2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Critical PoliciesTim Wawrzynczak
This patch adds support for DPTF Critical Policies, which are consist of Method definitions only. They are `_CRT` and `_HOT`, which are defined as temperature thresholds that, when exceeded, will execute a graceful suspend or a graceful shutdown, respectively. BUG=b:143539650 TEST=compiles Change-Id: I711ecdcf17ae8f6e653f33069201da4515ace85e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Passive PoliciesTim Wawrzynczak
This patch adds support for emitting the Thermal Relationship Table, as well as _PSV Methods, which together form the basis for DPTF Passive Policies. BUG=b:143539650 TEST=compiles Change-Id: I82e1c9022999b0a2a733aa6cd9c98a850e6f5408 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for generation of Active PoliciesTim Wawrzynczak
This change adds support for generating the different pieces of DPTF Active Policies. This includes the Active Relationship Table, in addition to _ACx methods. BUG=b:143539650 TEST=compiles Change-Id: Iea0ccbd96f88d0f3a8f2c77a7d0f3a284e5ee463 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07pci_ids: Add TGL & JSL IPU PCI IDsTim Wawrzynczak
Add PCI IDs for Intel's Image Processing Unit (IPU) for TGL & JSL Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I71dc95a6692e82ca25b0252b4f0789ee059df89f Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42811 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07acpi: add STA function to return external variableSugnan Prabhu S
This change adds support function to add STA function which returns an external variable. Change-Id: I31755a76ee985ee6059289ae194537d531270761 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42245 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05include/cpu/x86/lapic: Add support for x86_64Patrick Rudolph
Fix integer with different size to pointer conversion. Change-Id: I9c13892b2d79be12cc6bf7bc0a5e3a39b64032a1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42984 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04smbios: TYPE_NONE and TYPE_OTHER are already takenPatrick Georgi
Change-Id: Ic66f7c919a71cb53773d5056e5f756cd6faf4909 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43135 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04post_code: reorganize order of postcode definesSindhoor Tilak
Currently, the certain postcode values aren't in increasing order of values. The change, just reorganzies the defines in increasing order of the values Signed-off-by: Sindhoor Tilak <sindhoor@sin9yt.net> Change-Id: Id5f0ddc4593f689829ab9a7fdeebd5f66939bf79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04arch/x86/smbios: Add SMBIOS type8 dataBryantOu
Refer to section 7.9 Port Connector Information of DSP0134_3.3.0 to add type 8 data, the table of data should be ported according to platform design and MB silkscreen. Change-Id: I81e25d27c9c6717750edf1d547e5f4cfb8f1da14 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-02acpi_device: Replace polarity with active_low in acpi_gpio for GpioIoFurquan Shaikh
As per ACPI spec, GpioIo does not have any polarity associated with it. Linux kernel uses `active_low` argument within GPIO _DSD property to allow BIOS to indicate if the corresponding GPIO should be treated as active low. Thus, if GPIO has active high polarity or if it does not have any polarity associated with it, then the `active_low` argument is supposed to be set to 0. Having a `polarity` field in acpi_gpio seems confusing because GPIOs might not always have polarity associated with them. Example, in case of DMIC-select GPIO where 0 means select DMIC0 and 1 means select DMIC1, there is no polarity associated with the GPIO. Thus, it would be clearer for mainboard to use macros without having to specify a particular polarity. In order to enable mainboards to provide GPIO information without polarity for GpioIo usage, this change also adds `ACPI_GPIO_OUTPUT` and `ACPI_GPIO_INPUT` macros. BUG=b:157603026 Change-Id: I39d2a6ac8f149a74afeb915812fece86c9b9ad93 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02acpi_device: Add helper macros for setting acpi_gpio fieldsFurquan Shaikh
This change adds helper macros for initializing acpi_gpio fields for GpioIo/GpioInt objects. This allows dropping some redundant code for each macro to set the structure fields. Change-Id: Id0a655468759ed3035c6c1e8770e37f1275e344e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-01ACPI GNVS: Replace uses of smm_get_gnvs()Kyösti Mälkki
Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25arch/x86/smbios: Add more fields to be overriden for type 3 and 4Johnny Lin
For type 3, override chassis asset_tag_number with smbios_mainboard_asset_tag() and add two functions that can override chassis version and serial_number. For type 4 add smbios_processor_serial_number() to override serial_number. Tested on OCP Tioga Pass. Change-Id: I80c6244580a4428fab781d760071c51c7933abee Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-24ACPI: Replace smm_setup_structures()Kyösti Mälkki
Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-24ACPI: Add framework for GNVS initialisationKyösti Mälkki
Provide common initialisation point for setting up GNVS structure before first SMI is triggered. Change-Id: Iccad533c3824d70f6cbae52cc8dd79f142ece944 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42423 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22device/smbus_host: Declare common early SMBus prototypesKyösti Mälkki
Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22cpu/x86/lapic: Support x86_64 and clean up codePatrick Rudolph
Most LAPIC registers are 32bit, and thus the use of long is valid on x86_32, however it doesn't work on x86_64. * Don't use long as it is 64bit on x86_64, which breaks interrupts in QEMU and thus SeaBIOS wouldn't time out the boot menu * Get rid of unused defines * Get rid of unused atomic xchg code Tested on QEMU Q35 with x86_64 enabled: Interrupts work again. Tested on QEMU Q35 with x86_32 enabled: Interrupts are still working. Tested on Lenovo T410 with x86_64 enabled. Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36777 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22soc/amd/picasso/bootblock: Write EIP to secure S3Raul E Rangel
This change is required so we have a defined entry point on S3. Without this, the S3_RESUME_EIP_MSR register could in theory be written to later which would be a security risk. BUG=b:147042464 TEST=Resume trembyle and see bootblock start. coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 smm starting (log level: 8)... SMI# #6 SMI#: SLP = 0x0c01 Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) PSP: Prepare to enter sleep state 3... OK SMU: Put system into S3/S4/S5 Timestamp - start of bootblock: 18446744070740509170 coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 bootblock starting (log level: 8)... Family_Model: 00810f81 PMxC0 STATUS: 0x200800 SleepReset BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) Timestamp - end of bootblock: 18446744070804450274 VBOOT: Loading verstage. FMAP: area COREBOOT found @ c75000 (3715072 bytes) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 61b80 size cee4 PROG_RUN: Setting MTRR to cache stage. base: 0x04000000, size: 0x00010000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b0b0d0d576fc42b1628a4547a5c9a10bcbe9d37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-22cpu/x86/smm: Define APM_CNT_ROUTE_ALL_XHCIKyösti Mälkki
Change-Id: I0bc321f499278e0cdbfb40be9a2b2ae21828d2f4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22cpu/x86/smm: Define APM_CNT_NOOP_SMIKyösti Mälkki
Old (!PARALLEL_MP) cpu bringup uses this as the first control to do SMM relocation. Change-Id: I4241120b00fac77f0491d37f05ba17763db1254e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-18ACPI: Clean up some S3 related leftoversKyösti Mälkki
With RELOCATABLE_RAMSTAGE the backing up of low memory on S3 resume path was dropped. We forgot some things behind. Change-Id: I674f23dade0095e64619af0ae81e23368b1ee471 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-17treewide: Replace CONFIG(ARCH_xx) testsKyösti Mälkki
Once we support building stages for different architectures, such CONFIG(ARCH_xx) tests do not evaluate correctly anymore. Change-Id: I599995b3ed5c4dfd578c87067fe8bfc8c75b9d43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17device/pnp_ops.h: Use pnp.h functionsAngel Pons
With BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3ca080e700cf7b7f5b76cadddc7e41960413433c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42133 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17cpu/x86/smm: Add helper functions to verify SMM accessPatrick Rudolph
* Add a function to check if a region overlaps with SMM. * Add a function to check if a pointer points to SMM. * Document functions in Documentation/security/smm To be used to verify data accesses in SMM. Change-Id: Ia525d2bc685377f50ecf3bdcf337a4c885488213 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41084 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16cpu/x86: Define MTRR_CAP_PRMRRKyösti Mälkki
Followups will remove remaining cases of PRMRR_SUPPORTED and SMRR_SUPPORTED in the tree. Change-Id: I7f8c7d98f5e83a45cc0787c245cdcaf8fab176d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16sb,soc/intel: Replace smm_southbridge_enable_smi()Kyösti Mälkki
Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)Kyösti Mälkki
Change-Id: I8c4dc5ab91891de9737189bd7ae86df18d86f758 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16arch/x86: Declare global_smi_enable()Kyösti Mälkki
The call made at mp_ops.post_mp_init() generally uses four different names. Unify these with followups. smm_southbridge_enable(SMI_EVENTS) smm_southbridge_enable_smi() hudson_enable_smi_generation() enable_smi_generation() Furthermore, some platforms do not enable power button SMI early. It may be preferred to delay the enablement, but fow now provide global_smi_enable_no_pwrbtn() too. Change-Id: I6a28883ff9c563289b0e8199cd2ceb9acd6bacda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-16arch/x86: Create helper for APM_CNT SMI triggersKyösti Mälkki
Attempts to write to APM_CNT IO port should always be guarded with a test to verify SMI handler has been installed. Immediate followup removes redundant HAVE_SMI_HANDLER tests. Change-Id: If3fb0f1a8b32076f1d9f3fea9f817dd4b093ad98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41971 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15include: update cbmem_possibly_online for vboot_before_bootblockMartin Roth
cbmem is not online when vboot runs before the bootblock. Update the macro to reflect that. BUG=b:158124527 TEST=Build & boot psp_verstage on trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I6fb4ad04f276f2358ab9d4d210fdc7a34a93a5bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/42066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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