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2020-03-02soc/intel/denverton: Move PCI IDs to pci_ids.hFelix Singer
This patch moves the PCI ID definitions to pci_ids.h file and replaces every occurrence with the new names. The resulting binary doesn't differ from the one without this patch. Used documents: - Intel 337018 Change-Id: Ib7d2aae78c8877f3c9287d03b20a5620db293445 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-03-02soc/amd/picasso: Add PCI ID for Dali xHCIMarshall Dawson
soc//picasso is intended to be forward-compatible with the Dali APU, a Family 17h Models 20h-2Fh product. Add the one new device ID it has. See PPR document #55772 (still NDA only) for more information. Change-Id: I7e9b90bb00ae6f4a121f10b1467d2ca398ac860c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-25include/stdint.h: Remove old reference to ROMCCElyes HAOUAS
Change-Id: I00fdcee177c5d4b5e95bc3d0330fd8934eee2f0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2020-02-25soc/intel/common: Update Jasper Lake Device IDsMeera Ravindranath
Update Jasper Lake CPU, SA and PCH IDs. BUG=b:149185282 BRANCH=None TEST=Compilation for Jasper Lake board is working Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-21security/intel/stm: Check for processor STM supportEugene Myers
Check to ensure that dual monitor mode is supported on the current processor. Dual monitor mode is normally supported on any Intel x86 processor that has VTx support. The STM is a hypervisor that executes in SMM dual monitor mode. This check should fail only in the rare case were dual monitor mode is disabled. If the check fails, then the STM will not be initialized by coreboot. Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: I518bb2aa1bdec94b5b6d5e991d7575257f3dc6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-17soc/tigerlake: Add Device id for Tiger Lake Dual CoreSrinidhi N Kaushik
Add device id for Tiger Lake Dual core part. BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-02-17vboot: push clear recovery mode switch until BS_WRITE_TABLESJoel Kitching
Serves two purposes: (1) On some platforms, FSP initialization may cause a reboot. Push clearing the recovery mode switch until after FSP code runs, so that a manual recovery request (three-finger salute) will function correctly under this condition. (2) The recovery mode switch value is needed at BS_WRITE_TABLES for adding an event to elog. (Previously this was done by stashing the value in CBMEM_ID_EC_HOSTEVENT.) BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I30c02787c620b937e5a50a5ed94ac906e3112dad Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-08Add configurable ramstage support for minimal PCI scanningRonald G. Minnich
This CL has changes that allow us to enable a configurable ramstage, and one change that allows us to minimize PCI scanning. Minimal scanning is a frequently requested feature. To enable it, we add two new variables to src/Kconfig CONFIGURABLE_RAMSTAGE is the overall variable controlling other options for minimizing the ramstage. MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal PCI scanning. Some devices must be scanned in all cases, such as 0:0.0. To indicate which devices we must scan, we add a new mandatory keyword to sconfig It is used in place of on, off, or hidden, and indicates a device is enabled and mandatory. Mandatory devices are always scanned. When MINIMAL_PCI_SCANNING is enabled, ONLY mandatory devices are scanned. We further add support in src/device/pci_device.c to manage both MINIMAL_PCI_SCANNING and mandatory devices. Finally, to show how this works in practice, we add mandatory keywords to 3 devices on the qemu-q35. TEST= 1. This is tested and working on the qemu-q35 target. 2. On CML-Hatch Before CL: Total Boot time: ~685ms After CL: Total Boot time: ~615ms Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2020-02-05security/intel/stm: Add STM supportEugene Myers
This update is a combination of all four of the patches so that the commit can be done without breaking parts of coreboot. This possible breakage is because of the cross-dependencies between the original separate patches would cause failure because of data structure changes. security/intel/stm This directory contains the functions that check and move the STM to the MSEG, create its page tables, and create the BIOS resource list. The STM page tables is a six page region located in the MSEG and are pointed to by the CR3 Offset field in the MSEG header. The initial page tables will identity map all memory between 0-4G. The STM starts in IA32e mode, which requires page tables to exist at startup. The BIOS resource list defines the resources that the SMI Handler is allowed to access. This includes the SMM memory area where the SMI handler resides and other resources such as I/O devices. The STM uses the BIOS resource list to restrict the SMI handler's accesses. The BIOS resource list is currently located in the same area as the SMI handler. This location is shown in the comment section before smm_load_module in smm_module_loader.c Note: The files within security/intel/stm come directly from their Tianocore counterparts. Unnecessary code has been removed and the remaining code has been converted to meet coreboot coding requirements. For more information see: SMI Transfer Monitor (STM) User Guide, Intel Corp., August 2015, Rev 1.0, can be found at firmware.intel.com include/cpu/x86: Addtions to include/cpu/x86 for STM support. cpu/x86: STM Set up - The STM needs to be loaded into the MSEG during BIOS initialization and the SMM Monitor Control MSR be set to indicate that an STM is in the system. cpu/x86/smm: SMI module loader modifications needed to set up the SMM descriptors used by the STM during its initialization Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: ron minnich <rminnich@gmail.com>
2020-02-05pciexp: Add support for allocating PCI express hotplug resourcesJeremy Soller
This change adds support for allocating resources for PCI express hotplug bridges when PCIEXP_HOTPLUG is selected. By default, this will add 32 PCI subordinate numbers (buses), 256 MiB of prefetchable memory, 8 MiB of non-prefetchable memory, and 8 KiB of I/O space to any device with the PCI_EXP_SLTCAP_HPC bit set in the PCI_EXP_SLTCAP register, which indicates hot-plugging capability. The resource allocation is configurable, please see the PCIEXP_HOTPLUG_* variables in src/device/Kconfig. In order to support the allocation of hotplugged PCI buses, a new field is added to struct device called hotplug_buses. This is defaulted to zero, but when set, it adds the hotplug_buses value to the subordinate value of the PCI bridge. This allows devices to be plugged in and unplugged after boot. This code was tested on the System76 Darter Pro (darp6). Before this change, there are not enough resources allocated to the Thunderbolt PCI bridge to allow plugging in new devices after boot. This can be worked around in the Linux kernel by passing a boot param such as: pci=assign-busses,hpbussize=32,realloc This change makes it possible to use Thunderbolt hotplugging without kernel parameters, and attempts to match closely what our motherboard manufacturer's firmware does by default. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I500191626584b83e6a8ae38417fd324b5e803afc Reviewed-on: https://review.coreboot.org/c/coreboot/+/35946 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28drivers/spi/spi_flash: remove spi flash namesAaron Durbin
The names of each spi flash cause quite a bit of bloat in the text size of each stage/program. Remove the name entirely from spi flash in order to reduce overhead. In order to pack space as closely as possible the previous 32-bit id and mask were split into 2 16-bit ids and masks. On Chrome OS build of Aleena there's a savings of >2.21KiB in each of verstage, romstage, and ramstage. Change-Id: Ie98f7e1c7d116c5d7b4bf78605f62fee89dee0a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-28commonlib: Add commonlib/bsdJulius Werner
This patch creates a new commonlib/bsd subdirectory with a similar purpose to the existing commonlib, with the difference that all files under this subdirectory shall be licensed under the BSD-3-Clause license (or compatible permissive license). The goal is to allow more code to be shared with libpayload in the future. Initially, I'm going to move a few files there that have already been BSD-licensed in the existing commonlib. I am also exracting most contents of the often-needed <commonlib/helpers.h> as long as they have either been written by me (and are hereby relicensed) or have an existing equivalent in BSD-licensed libpayload code. I am also relicensing <commonlib/compression.h> (written by me) and <commonlib/compiler.h> (same stuff exists in libpayload). Finally, I am extracting the cb_err error code definitions from <types.h> into a new BSD-licensed header so that future commonlib/bsd code can build upon a common set of error values. I am making the assumption here that the enum constants and the half-sentence fragments of documentation next to them by themselves do not meet the threshold of copyrightability. Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-22soc/intel/common: Add Elkhartlake Device IDsTan, Lean Sheng
Add Elkhartlake CPU, SA and PCH IDs. EHL PCH is code named as MCC. Also add a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I03f15832143bcc3095a3936c65fbc30a95e7f0f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38489 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDsGaggery Tsai
This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for 10-Core ID. Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-18src/include: Fix typosElyes HAOUAS
Change-Id: Ia8e6e5bd5ac2565263d81df8ca81d62436a3301f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18cbfs: Remove locator conceptJulius Werner
When vboot was first integrated into CBFS it was still part of Google vendorcode. So to not directly tie custom vendorcode into the core CBFS library, the concept of cbfs_locator was introduced to decouple core code from an arbitrary amount of platform-specific implementations that want to decide where the CBFS can be found. Nowadays vboot is a core coreboot feature itself, and the locator concept isn't used by anything else anymore. This patch simplifies the code by removing it and just calling vboot from the CBFS library directly. That should make it easier to more closely integrate vboot into CBFS in the future. Change-Id: I7b9112adc7b53aa218c58b8cb5c85982dcc1dbc0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-17drivers/spi/spi_flash: organize spi flash by sector topologyAaron Durbin
By grouping the spi flash parts by their {vendor, sector topology} tuple one can use a common probe function for looking up the part instead of having per-vendor probe functions. Additionally, by grouping by the command set one can save more space as well. SST is the exception that requires after_probe() function to unlock the parts. 2KiB of savings in each of verstage, romstage, and ramstage on Aleena Chrome OS Build. Change-Id: I9cc20ca0f3d0a1b97154b000c95ff2e7e87f3375 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-17drivers/spi/spi_flash: introduce common spi_flash_part_id objectAaron Durbin
To further drive to a common approach for describing the spi flash parts in the drivers add spi_flash_part_id object. All the drivers are updated to utilize the new object. Additionally, the driver_private is also not needed in the spi_flash object. A Chrome OS build of Aleena provides 960 byte saving of text. A subsequent patch will save more memory. Change-Id: I9c0cc75f188ac004ab647805b9551bf06a0c646b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-16drivers/spi/spi_flash: separate out protection opsAaron Durbin
Put the write protection into its own object. This allows for easier future reuse of objects in future consolidation patches. It's also possible to eliminate the code implmementing these in the future if the platform doesn't require it. For now leave current behavior as-is. The names of the callbacks were shortened as they are now in the spi_flash_protection_ops object which is a new field in the spi_flash object. Change-Id: I2fec4e4430709fcf3e08a55dd36583211c035c08 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-14sb/intel/common: Declare common smbus_base() and enable_smbus()Kyösti Mälkki
This avoids including platform-specific headers with different filenames from common code. Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-14drivers/pc80/rtc: Clean up some POST_CODE_EXTRA useKyösti Mälkki
Change-Id: I5ecfa0860a28547f76a72592a8d07bca67822217 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38188 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14console/post: Split parts to arch/Kyösti Mälkki
Both IO port and cmos are currently arch/x86 only features. Change-Id: I010af3f645c0be38dd856657874c36103aebbdc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38187 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10console/post: Move cmos_post_code() under pc80/rtcKyösti Mälkki
We should keep console/ somewhat arch-agnostic. Change-Id: I4465888023ba5ae0706b5e98e541c40f975d11e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38186 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10drivers/pc80/rtc: Move sanitize_cmos()Kyösti Mälkki
Implementation depends on USE_OPTION_TABLE. Change-Id: If7f8f478db3214842b6cc60cd77b4ea81cab6e3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38195 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10drivers/spi/spi_flash: explicitly handle STMicro deep power stateAaron Durbin
In order to provide more consistent probing in future refactorings, pull out the release from deep sleep path in STMicro's SPI flash probing function. Call that function explicitly when RDID doesn't return anything at all. The old STMicro parts, even if supporting RDID, won't decode that instruction while in a deep power down state. Instead of re-issuing RDID after the successful wake assume the id fixup is valid. Change-Id: I46c47abcfb1376c1c3ce772f6f232857b8c54202 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-09sb/intel/common: Add smbus_set_slave_addr()Kyösti Mälkki
Change-Id: I7dddb61fab00e0f4f67d4eebee0cfe8dcd99f4ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38230 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09sb/intel/common: Add smbus_host_reset()Kyösti Mälkki
Change-Id: I3f6000df391295e2c0ce910a2a919a1dd3333519 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09device,sb/intel: Move SMBus host controller prototypesKyösti Mälkki
Also change some of the types to match the register widths of the controller. It is expected that these prototypes will be used with SMBus host controllers inside AMD chipsets as well, thus the change of location. Change-Id: I88fe834f3eee7b7bfeff02f91a1c25bb5aee9b65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38226 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09lib/spd_bin,soc/intel/common: Move get_spd_smbus()Kyösti Mälkki
Only smbuslib.c and spd_bin.c share the same prototypes for SMBUS functions. Therefore, get_spd_smbus() currently only works with soc/intel/.../smbuslib.c and can be implemented there locally. This allows removal of <device/early_smbus.h>. Change-Id: Ic2d9d83ede6388a01d40c6e4768f6bb6bf899c00 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09drivers/pc80/rtc: Remove duplicate cmos_chksum_valid()Kyösti Mälkki
Change-Id: I5a4b86921876c24cd1d310b674119b960c3d2fd6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38194 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08src/include: Fix typosElyes HAOUAS
Change-Id: I52302e99708bca2f1e5e45f52cacd42e05a5fbd5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37567 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08soc/intel/cannonlake: Add Comet Lake H SA 4+2 Device IDJamie Chen
This patch adds CML-H 4+2 SA DID into systemagent.c and report platform. According to doc #605546: CML-H (4+2) R1: 9B64h BUG:none BRANCH:none TEST:build no error Change-Id: I5bac6173a84a11abd2ce17f82854fbb14fb8558b Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2020-01-07drivers/pc80/rtc: Remove stub for sanitize_cmos()Kyösti Mälkki
We only have a single call-site for this. Change-Id: I7ab19c6ea4ef01334f4d229c5636b64f99c86119 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38182 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07drivers/pc80/rtc: Remove stub for cmos_post_init()Kyösti Mälkki
We only have a single call-site for this. Change-Id: Ia05a762691351b37cc59b39222fec737b29e913c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-07drivers/pc80/rtc: Clean up some headersKyösti Mälkki
Change-Id: I5b3f1da6581dd80264aaa9618227ac64e1966e8d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38180 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07drivers/pc80/rtc: Clean up some inlined functionsKyösti Mälkki
Change-Id: Ie73797b4e9a09605a0685f0b03cb85e9a3be93ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-07lib/crc_byte: Add CRC32 implementationPatrick Rudolph
* Add CRC32 using polynomial 0x04C11DB7 + Add macro to caculate CRC of a buffer Change-Id: If98e4e12bb53a6e5123e94e8cdffde1eb3bc4b4b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37753 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-06drives/spi_flash: add spi_flash_cmd_write_page_program()Aaron Durbin
The SPI flashes that support page programming mode had duplicated the logic for writing in every driver. Add spi_flash_cmd_write_page_program() and use the common implementation to reduce code size that comes from duplication. The savings is ~2.5KiB per stage where the spi flash drivers are utilized. Change-Id: Ie6db03fa8ad33789f1d07a718a769e4ca8bffe1d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-01-06drivers/pc80/rtc: Swap cmos_write32() parameter orderKyösti Mälkki
Make it consistent with the more used cmos_write(). Change-Id: I9cf643c770e9819de08dbede48b73f3d4fe15bd7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38178 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-05pci_ids: Correct whitespace for all AMD, ATI, National SemiMarshall Dawson
Convert spaces to tabs to match surrounding definitions and fix alignment for AMD products and prior assets. Change-Id: I37f1b7826afab8e224fb2d411247d77ea32664df Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-04device/smbus: Drop unused smbus_set_link()Kyösti Mälkki
I expect it to be easier to just remodel the support for i2c multiplexers instead. Besides, there was no proper bounds for pbus_num when accessing pbus_a[]. Change-Id: I17f33b308c01e48bc03b142550535c32862442ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-04device/smbus: Drop SMBUS_HAS_AUX_CHANNELSKyösti Mälkki
The guarded prototypes are no longer implemented in the tree. Change-Id: I5bfedde2aaf691826e7537eceb8578a855800ea2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-03spi-generic: remove SPI_FLASH_SECTOR_ERASE_TIMEOUT_MSAaron Durbin
There was one user of SPI_FLASH_SECTOR_ERASE_TIMEOUT_MS, southbridge/intel/common/spi.c. Remove the define and encode the 1 second timeout that it was wanting at the single use site. Change-Id: If33a1a04bc4d3441e90bf0ca305ddf71c4f8bb88 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-01-03device/early_smbus: Drop unused function parameterKyösti Mälkki
Change-Id: I2d62c470c5389af3b10e47ca5e721b78ff16bc79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-03device/early_smbus: Remove unused prototypesKyösti Mälkki
Change-Id: Iecc6591244781e092132a058fe888f3bdd78cc50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-02lib/malloc: Implement a simple free() only for last malloc()Bora Guvendik
Implement a free() that supports only the last malloc(). Rewind the heap to the last allocation point if the ptr to be freed is matching the end of heap before last malloc(). With current situation, since free() is no-op, every call to malloc() is a memory leak. BUG=b:140124451 TEST=Wrote a test function to do malloc and free operations. Change-Id: I6d43cf54b79e6897cf6882335730b2310e4eae45 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-01-02drivers/pc80/mc146818rtc: Remove read_option_lowlevel()Kyösti Mälkki
This was a workaround for romcc. Change-Id: I34f41390afbd88f3ace7003fd18c2edd56712a67 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37954 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-02src/include: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I9e5d18739e7c5b5c742a905ac482529c7e0866df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37827 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31src: Remove some romcc workaroundsJacob Garber
Now that romcc is gone, move cmos_post_init() into post.c, and remove some preprocessor workarounds. Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-19 00:46:01 +0000