coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2016-09-19	arch/x86,lib: make cbmem console work in postcar stage	Aaron Durbin
2016-05-21	program.ld: Don't exclude sbe region from verstage	Stefan Reinauer
2016-04-30	lib/reg_script: Allow multiple independent handlers	Lee Leahy
2016-04-16	program.ld: make sure that zeroptr isn't assigned to debug sections	Patrick Georgi
2016-03-23	arch/x86: introduce postcar stage/phase	Aaron Durbin
2016-01-28	Provide a gcc-safe zero pointer	Patrick Georgi
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-28	program.ld: terminate ALIGN statement	Patrick Georgi
2015-09-22	linking: link bootblock.elf with .data and .bss sections again	Aaron Durbin
2015-09-17	linking: Repair special treatments for non-x86 bootblocks	Julius Werner
2015-09-09	x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE	Aaron Durbin
2015-09-09	rmodule: use program.ld for linking	Aaron Durbin
2015-09-09	x86: link romstage like the other architectures	Aaron Durbin
2015-09-09	linking: lay the groundwork for a unified linking approach	Aaron Durbin