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2020-10-30lib/libpayload: Replace strapping_ids with new board configuration entryTim Wawrzynczak
There are currently 3 different strapping ID entries in the coreboot table, which adds overhead. The new fw_config field is also desired in the coreboot table, which is another kind of strapping id. Therefore, this patch deprecates the 3 current strapping ID entries (board ID, RAM code, and SKU ID), and adds a new entry ("board_config") which provides board ID, RAM code, SKU ID, as well as FW_CONFIG together. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1ecec847ee77b72233587c1ad7f124e2027470bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/46605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-30fw_config: Make fw_config_get() publicTim Wawrzynczak
Further patches will make use of this raw 64-bit value. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I161893c09da6a44265299f6ae3c3a81249a96084 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46604 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30fw_config: Convert fw_config to a 64-bit fieldTim Wawrzynczak
We all knew this was coming, 32 bits is never enough. Doing this early so that it doesn't affect too much code yet. Take care of every usage of fw_config throughout the codebase so the conversion is all done at once. BUG=b:169668368 TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG and verify the console print contained that bit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30cbfs: Hook up to new CBFS implementationJulius Werner
This patch hooks coreboot up to the new commonlib/bsd CBFS implementation. This is intended as the "minimum viable patch" that makes the new implementation useable with the smallest amount of changes -- that is why some of this may look a bit roundabout (returning the whole metadata for a file but then just using that to fill out the rdevs of the existing struct cbfsf). Future changes will migrate the higher level CBFS APIs one-by-one to use the new implementation directly (rather than translated into the results of the old one), at which point this will become more efficient. Change-Id: I4d112d1239475920de2d872dac179c245275038d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38422 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26lib/edid: Add missing name descriptor presence flagJakub Czapiga
EDID parser internal flag c->has_name_descriptor was never set. It was causing decode_edid() function to return NON_CONFORMANT instead of CONFORMANT even when EDID frame was correct. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ifdc723b892a0885cfca08dab1a5ef961463da289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-22drivers/smmstore: Implement SMMSTORE version 2Patrick Rudolph
SMMSTORE version 2 is a complete redesign of the current driver. It is not backwards-compatible with version 1, and only one version can be used at a time. Key features: * Uses a fixed communication buffer instead of writing to arbitrary memory addresses provided by untrusted ring0 code. * Gives the caller full control over the used data format. * Splits the store into smaller chunks to allow fault tolerant updates. * Doesn't provide feedback about the actual read/written bytes, just returns error or success in registers. * Returns an error if the requested operation would overflow the communication buffer. Separate the SMMSTORE into 64 KiB blocks that can individually be read/written/erased. To be used by payloads that implement a FaultTolerant Variable store like TianoCore. The implementation has been tested against EDK2 master. An example EDK2 implementation can be found here: https://github.com/9elements/edk2-1/commit/eb1127744a3a5d5c8ac4e8eb76f07e79c736dbe2 Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-19lib/imd: move struct definitions to a new header fileJakub Czapiga
Make IMD private structures definitions accessible by other units. To test IMD API correctness there is a need to access its internal structure. It is only possible when private implementation is visible in testing scope. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Iff87cc1990426bee6ac3cc1dfa6f85a787334976 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-10-13lib/cbfs: deserialize cbfs_stage objects correctlyAaron Durbin
cbfstool emits cbfs_stage objects in little endian encoding. However, big endian targets then read the wrong values from these objects. To maintain backwards compatibility with existing cbfs objects add in the little endian deserialization. Change-Id: Ia113f7ddfa93f0ba5a76e0397f06f9b84c833727 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Marty E. Plummer <hanetzer@startmail.com>
2020-10-09trogdor: Modify DDR training to use mrc_cacheShelley Chen
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table. BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not. Boot into recovery two consecutive times and make sure memory training occurs on both boots. Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-09lib/spd: respect spd memory part name overrideNick Vaccaro
The BIOS log was looking in the spd data for the part name, but part names are stripped from generic SPDs. For these cases, a mainboard can override the dram part number string, so the spd logging code needs to check for an override string when logging the dram part number. Change print_spd_info() to use an override string if declared. BUG=b:168724473 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer2 and verify that the BIOS log shows a part name when logging SPD information: SPD: module part number is K4U6E3S4AA-MGCL I also modified volteer to not override the part name and verified that this change did as expected and printed a blank string. Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45459 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08lib/fw_config: change BOOT_STATE_INIT_ENTRY to be BS_DEV_INIT_CHIPSNick Vaccaro
Make boot state init run before the init_chips code. This allows for correcting tbt settings at a stage earlier than devicetree parsing. BUG=b:167983038 TEST=none Change-Id: I8364746ba311575e7de93fa25241ffef7faf35b4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45961 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05lib/spd_bin: add LPDDR4X case to spd_get_name()Nick Vaccaro
Add case for LPDDR4x to spd_get_name(). BUG=b:169800932, b:168724473 TEST=none Change-Id: I6bae373468b8ad5ae0a6b8dd6bbe14143afb85af Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45886 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()Nick Vaccaro
Consolidate all weak declarations of mainboard_get_dram_part_num() to instead use the common definition in lib/spd_bin.c. BUG=b:168724473 TEST="emerge-volteer coreboot && emerge-nocturne coreboot && emerge-dedede coreboot" and verify build succeeds without error. Change-Id: I322899c080ab7ebcf1cdcad3ce3dfa1d022864d1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-05lib/ubsan.c: Remove GCC 5.x workaroundAngel Pons
The coreboot toolchain has been using a newer GCC version for a while already. This code is build-tested from commit 13cd145e02e onwards. Change-Id: Ic324b503878c73e4560d4d8f2e0d38ecb595b8fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45822 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-26lib/Makefile.inc: fix name of config stringPaul Fagerburg
The config string is HAVE_SPD_IN_CBFS, without the "BIN". Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: I728f64b2dd93b0e3947983b9b3701e185feff571 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-23lib/Makefile.inc: drop redundant conditional on CONFIG_HAVE_SPD_IN_CBFSMichael Niewöhner
Change-Id: I56d13540b2c6b66d5c674ae3d5bab0ac9505df58 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45154 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23lib/Makefile.inc: fail build when SPD would be emptyMichael Niewöhner
Add a check to be sure that at least one SPD file will be added and fail the build when the resulting spd.bin would be empty. Change-Id: Ic6db1dbe5fed5f242e408bcad4f36dda1b1fa1b4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45131 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFSMichael Niewöhner
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is used for, so rename it to HAVE_SPD_BIN_IN_CBFS. Change-Id: I4004c48da205949e05101039abd4cf32666787df Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22src/lib/bootblock.c: make bootblock_main_with_timestamp publicKangheui Won
bootblock_main_with_timestamp function allows to proceed with existing timestamp table. Apparently we never needed this, but Zork runs verstage in the PSP before bootblock. It'd be useful if we can grab timestamps for verstage from PSP and merge with coreboot timestamps. Making it non-static will enable us to do that. BUG=b:154142138, b:159220781 BRANCH=zork TEST=build firmware for zork Change-Id: I061c3fbb652c40bafa0a007aa75f2a82680f5e0a Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-22soc/amd/picasso: record timestamps in psp_verstageKangheui Won
Verstage in PSP used stub for timestamps since we didn't know about clock. Now we figured out clock source so we can enable timestamp functions. BRANCH=zork BUG=b:154142138, b:159220781 TEST=build without CONFIG_PSP_VERSTAGE_FILE, flash and boot Change-Id: I431a243878e265b68783f54ee9424bb1d4fe03c1 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-16region_file_update_data_arr: Modify region_file with array of buffersShelley Chen
Add region_file_update_data_arr, which has the same functionality as region_file_update_data, but accepts mutliple data buffers. This is useful for when we have the mrc_metadata and data in non-contiguous addresses, which is the case when we bypass the storing of mrc_cache data into the cbmem. BUG=b:150502246 BRANCH=None TEST=reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again. Change-Id: Ia530f7d428b9b07ce3a73e348016038d9daf4c15 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45407 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14lib/fmap: add ENV_SMM check to setup_preram_cacheJosie Nordrum
Add check in setup_preram_cache to return if ENV_SMM is true. This avoids false warning that post-RAM FMAP is accessed too early caused by ENV_ROMSTAGE_OR_BEFORE evaluation in SMI handler. BUG=b:167321319 BRANCH=None TEST=None Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I3a4c199c42ee556187d6c4277e8793a36e4d493b Reviewed-on: https://review.coreboot.org/c/coreboot/+/45274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-10lib/Makefile.inc: fix hex-to-bin conversion of SPD filesMichael Niewöhner
This fixes the hex-to-bin conversion command, used to generated binary SPD files from hexdumps. An issue that only appeared on one of my systems, where conversion of '01 02 03' to binary resulted in \x01\x32\x03 instead of \x01\x02\x03: for c in 01 02 03; do printf $(printf '\%o' 0x$c); done | xxd -g 1 00000000: 01 32 03 .2. The reason for this was that the syntax in lib/Makefile.inc is wrong, because the backslash must be escaped due to chaining two printf commands. Change-Id: I36b0efac81977e95d3cc4f189c3ae418379fe315 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08lib/Kconfig: Drop obsolete help text from GENERIC_SPD_BINMichael Niewöhner
SMBus code is linked unconditionally since commit 0e3c59e. This change drops that obsolete part from the help text. Change-Id: I603ab012760684021be1b5eca5d0ddff69463b79 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-31fw_config: Add caching to successfully probed fieldsTim Wawrzynczak
Add a backing cache for all successfully probed fw_config fields that originated as `probe` statements in the devicetree. This allows recall of the `struct fw_config` which was probed. BUG=b:161963281 TEST=tested with follower patch Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0d014206a4ee6cc7592e12e704a7708652330eaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/44782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-27symbols: Change implementation details of DECLARE_OPTIONAL_REGION()Julius Werner
It seems that GCC's LTO doesn't like the way we implement DECLARE_OPTIONAL_REGION(). This patch changes it so that rather than having a normal DECLARE_REGION() in <symbols.h> and then an extra DECLARE_OPTIONAL_REGION() in the C file using it, you just say DECLARE_OPTIONAL_REGION() directly in <symbols.h> (in place and instead of the usual DECLARE_REGION()). This basically looks the same way in the resulting object file but somehow LTO seems to like it better. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I6096207b311d70c8e9956cd9406bec45be04a4a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-08-26lib/imd: Prohibit removing imd_entry covering root regionJan Dabros
Removing entry covering root region leads to situation where num_entries counter is set to 0. This counter is further decremented in function obtaining address to last entry (see root_last_entry()). Such negative number may be further used as an index to the table. Current implementation may lead to crash, when user removes last entry with imd_entry_remove() and then calls for example imd_entry_add(). Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I6ff54cce55bf10c82a5093f47c7f788fd7c12d3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-26lib/imd: Fix imdr_recover for small regionsJan Dabros
One of the checks inside imdr_recover() was written with the assumption that imdr limit is always aligned to LIMIT_ALIGN. This is true only for large allocations, thus may fail for small regions. It's not necessary to check if root_pointer is under the limit, since this is implicitly verified by imdr_get_root_pointer(). Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I25d6291301797d10c6a267b5f6e56ac38b995b7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/44667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-26lib/imd: Improve check to filter out 0-size imd_entriesJan Dabros
Previously it was allowed to create an imd_entry with size 0, however algorithm sets the offset of such entry to the exact same address as the last registered entry. Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: Ifa2cdc887381fb0d268e2c199e868b038aafff5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-26lib/imd: Add an extra check for root_sizeJan Dabros
Add a check that root_size provided by the caller accounts for one imd_entry necessary for covering imd_root region. Without this, we may end up with writing on unallocated memory. Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I0a39d56f7a2a6fa026d259c5b5b78def4f115095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-26include/imd: Improve API documentationJan Dabros
Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I8261c7d933435ba9f29fc3172cdfe8bcae5c1af9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-26lib/imd: Remove redundant code in imd.cAnna Karas
Get rid of the second check whether r is NULL (this is already done by imdr_has_entry()). Signed-off-by: Anna Karas <aka@semihalf.com> Change-Id: Ibee1664ee45b29d36e2eaaa7dff4c7cc1942010b Reviewed-on: https://review.coreboot.org/c/coreboot/+/44663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-26src/lib: Fix a mistake in a comment in imd.cAnna Karas
Remove the repetition from the comment. Signed-off-by: Anna Karas <aka@semihalf.com> Change-Id: Ibe6e38636b96b6d8af702b05a822995fd576b2fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/44662 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21lib: Update fmap cache error for psp_verstageMartin Roth
The assumption was that the fmap cache would be initialized in bootblock, otherwise an error is shown. This error is showing up in psp_verstage when the fmap cache is initialized there, so create a new ENV value for ENV_INITIAL_STAGE. BUG=None TEST=Boot, see that error message is gone from psp_verstage Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I142f2092ade7b4327780d423d121728bfbdab247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43488 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21arch/x86: Add support for ASan to memory functionsHarshit Sharma
Compiler's instrumentation cannot insert asan memory checks in case of memory functions like memset, memcpy and memmove as they are written in assembly. So, we need to manually check the memory state before performing each of these operations to ensure that ASan is triggered in case of bad access. Change-Id: I2030437636c77aea7cccda8efe050df4b77c15c7 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-21lib: Add ASan support to romstage on x86 archHarshit Sharma
This patch adds ASan support to romstage on x86 architecture. A Kconfig option is added to enable ASan in romstage. Compiler flags are updated. A memory space representing the shadow region is reserved in linker section. And a function call to asan_init() is added to initialize shadow region when romstage loads. Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-21lib: Add ASan support to ramstage on x86 archHarshit Sharma
This patch adds address sanitizer module to the library and reserves a linker section representing the shadow region for ramstage. Also, it adds an instruction to initialize shadow region on x86 architecture when ramstage is loaded. Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-21lib: Update ASan compiler flags and Kconfig help textHarshit Sharma
An additional compiler flag is added to make use of the shadow offset callback feature we introduced in our GCC patch. Also, a comment is added to tell user that this GCC patch needs to be applied in order to use ASan. Change-Id: Ia187e4991bf808f4ae137eff0ffdb9baea0085e9 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-21lib: Add ASan stubHarshit Sharma
Add a Kconfig option to enable address sanitizer on x86 architecture. Create ASan dummy functions. And add relevant gcc flags to compile ramstage with ASan. Change-Id: I6d87e48b6786f02dd46ea74e702f294082fd8891 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-18src: Remove unused 'include <stddef.h>Elyes HAOUAS
Change-Id: Iae1e875b466f8a195653d897efa1b297c61ad0a5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41912 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17lib/imd_cbmem.c: Add a helper function to indicate that cbmem is readyArthur Heymans
This can be used in romstage in particular to know if dram is ready. Change-Id: I0231ab9c0b78a69faa762e0a97378bf0b50eebaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-06gpio: Pull down HiZ pins after reading tristate GPIO strappingJulius Werner
People who know a lot more about electrons and stuff than I do tell me that leaving a HiZ pin floating without a pull resistor may waste power. So if we find a pin to be HiZ when reading tristate strapping GPIOs, we should make sure the internal pull-down is enabled when we're done with it. (For pins that are externally pulled high or low, we should continue to leave the internal pull disabled instead.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1669823c8a7faab536e0441cb4c6cfeb9f696189 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44253 Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Alexandru Stan <amstan@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04src/lib: Remove unused function parameters in imd.cAnna Karas
Remove const struct imd *imd and const struct imdr *imdr parameters from the prototypes of imdr_entry_size(), imd_entry_size() and imd_entry_id() functions since they are not used anywhere. Signed-off-by: Anna Karas <aka@semihalf.com> Change-Id: I6b43e9a5ae1f1d108024b4060a04c57f5d77fb55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43999 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03lib/gcov: Remove assert(0)Patrick Georgi
This follows CB:44047 which probably missed this because it's a custom assert macro (in code that has only recently been added to build checks). Without this change, building with gcov fails because gcc_assert(0) can be build-time verified (as introduced by CB:44044) while we need runtime failure semantics here. Change-Id: I71a38631955a6a45abe90f2b9ce3a924cc5d6837 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-08-03lib/string: Add standard strstr() functionJes Klinke
Adding implementation of standard library strstr() See https://review.coreboot.org/c/coreboot/+/43741 for context. Change-Id: I63e26e98ed2dd15542f81c0a3a5e353bb93b7350 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-31lib/ubsan.c: Update error handlers for current toolchain's GCCAngel Pons
Looks like UBSan isn't being build-tested, and the toolchain has been updated several times since UBSan support was added. Unexpectedly, it no longer builds when using GCC from the current toolchain version. To fix this, rename an error handler and add a newly-introduced handler for `__ubsan_handle_pointer_overflow`, which works like the existing handlers. A config file to allow build-testing UBSan is added later. Change-Id: I5980730d8d22fa1d0512846c203004723847cc6d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30lib/bootmem.c: Improve bootmem_allocate_buffer algorithmJan Dabros
Since regions in bootmem are sorted by increasing base address, we may bail out of the search loop as soon as the region_base is bigger than the max address allowed. Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I44b44bf9618fd0615103cbf74271235d61d49473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43512 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29lib/libgcov.c: Do not redefine `alloca`Angel Pons
This is already defined in <commonlib/helpers.h> and it gets included implicitly by some other header. Fixes building with code coverage. Change-Id: Id2dc6cc34b6f1d351d8e1b52d8cc4ada8666c673 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-28ACPI S3: Clean up resume pathKyösti Mälkki
Remove the obscure path in source code, where ACPI S3 resume was prohibited and acpi_resume() would return and continue to BS_WRITE_TABLES. The condition when ACPI S3 would be prohibited needs to be checked early in romstage already. For the time being, there has been little interest to have CMOS option to disable ACPI S3 resume feature. Change-Id: If5105912759427f94f84d46d1a3141aa75cbd6ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-14src: Remove unused 'include <types.h>'Elyes HAOUAS
Files found using: diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<' Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 05:17:39 +0000