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This eliminates the use of do_div() in favor of using libgcc
functions.
This was tested by building and booting on Google Snow (ARMv7)
and Qemu (x86). printk()s which use division in vtxprintf() look good.
Change-Id: Icad001d84a3c05bfbf77098f3d644816280b4a4d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2606
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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A board without HAVE_ACPI_RESUME did not build with
COLLECT_TIMESTAMPS enabled as `cbmem.c` was not built.
Change-Id: I9c8b575d445ac566a2ec533d73080bcccc3dfbca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2549
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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It's been on for all boards per default since several years now
and the old code path probably doesn't even work anymore. Let's
just have one consistent way of doing things.
Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Entry point in payload segment header is a 64 bit integer (ntohll). The debug
message is currently reading that as a 32 bit integer (which will produce
00000000 for most platforms).
Change-Id: I931072bbb82c099ce7fae04f15c8a35afa02e510
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2535
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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Pulling CBFS fix from libpayload: http://review.coreboot.org/#/c/2455/2
get_cbfs_header expects CBFS_HEADER_INVALID_ADDRESS (0xffffffff)
instead of NULL when something is wrong.
Also, fix typo.
Change-Id: I7f393f7c24f74a3358f7339a3095b0d845bdc02d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2457
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The order of some printk arguments were reversed.
Change-Id: I5e8f70b79050b92ebe8cfa5aae94b6cd1a5fd547
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2364
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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For x86, the old CBFS search behavior was to bypass bootblock and we should keep
that. This will speed up searching if a file does not exist in CBFS.
For arm, the size in header is correct now so we can remove the hack by
CONFIG_ROM_SIZE.
Change-Id: I541961bc4dd083a583f8a80b69e293694fb055ef
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2292
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Some variables are using incorrect data type in debug messages.
Also corrects a typo (extra 'x').
Change-Id: Ia3014ea018f8c1e4733c54a7d9ee196d0437cfbb
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2294
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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For ARM platform, the bootblock may need more C source files to initialize
UART / SPI for loading romstage. To preventing making complex and implicit
dependency by using #include inside bootblock.c, we should add a new build class
"bootblock".
Also #ifdef __BOOT_BLOCK__ can be used to detect if the source is being compiled
for boot block.
For x86, the bootblock is limited to fewer assembly files so it's not using this
class. (Some files shared by x86 and arm in top level or lib are also changed
but nothing should be changed in x86 build process.)
Change-Id: Ia81bccc366d2082397d133d9245f7ecb33b8bc8b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2252
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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LZMA decode library used to retrieve output size by:
outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
'src' is aligned but LZMA_PROPERTIES_SIZE may refer to an unaligned address like
src+5, and using that as integer pointer may fail on platforms like ARM. Also
this will fail on systems using big-endian (outSize was encoded in
little-endian).
To fix this, reconstruct outSize in little-endian way.
Change-Id: If678e735cb270c3e5e29f36f1fad318096bf7d59
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2246
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Summary:
Isolate CBFS underlying I/O to board/arch-specific implementations as
"media stream", to allow loading and booting romstage on non-x86.
CBFS functions now all take a new "media source" parameter; use
CBFS_DEFAULT_MEDIA if you simply want to load from main firmware.
API Changes:
cbfs_find => cbfs_get_file.
cbfs_find_file => cbfs_get_file_content.
cbfs_get_file => cbfs_get_file_content with correct type.
CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM,
the ROM may come from USB, UART, or SPI -- any serial devices and not available
for memory mapping.
To support these devices (and allowing CBFS to read from multiple source
at the same time), CBFS operations are now virtual-ized into "cbfs_media". To
simplify porting existing code, every media source must support both "reading
into pre-allocated memory (read)" and "read and return an allocated buffer
(map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*"
provides simple memory mapping simulation.
Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA
is defined for CBFS functions to automatically initialize a per-board default
media (CBFS will internally calls init_default_cbfs_media). Also revised CBFS
function names relying on memory mapped backend (ex, "cbfs_find" => actually
loads files). Now we only have two getters:
struct cbfs_file *entry = cbfs_get_file(media, name);
void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type);
Test results:
- Verified to work on x86/qemu.
- Compiles on ARM, and follow up commit will provide working SPI driver.
Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2182
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I96d41882c92e577ce816264c493376d2f2d950f6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2181
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
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.. to reflect the recent changes w.r.t avoiding
trouble with the coreboot pre-commit hooks.
and fix two whitespace errors.
Change-Id: I6c94e95dd439940cf3b44231c8aab5126e9d45c7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2158
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
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Make the comments match what pre-commit-hook wants.
Change-Id: Ib99a6583f97221df3638bd3b7723f51d5f9c223c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2143
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to provide some insight on what code is executed during
coreboot's run time and how well our test scenarios work, this
adds code coverage support to coreboot's ram stage. This should
be easily adaptable for payloads, and maybe even romstage.
See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
more information.
To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
support") in Kconfig, and recompile coreboot. coreboot will then
store its code coverage information into CBMEM, if possible.
Then, run "cbmem -CV" as root on the target system running the
instrumented coreboot binary. This will create a whole bunch of
.gcda files that contain coverage information. Tar them up, copy
them to your build system machine, and untar them. Then you can
use your favorite coverage utility (gcov, lcov, ...) to visualize
code coverage.
For a sneak peak of what will expect you, please take a look
at http://www.coreboot.org/~stepan/coreboot-coverage/
Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2052
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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ARM does not need them, and they're causing trouble
Change-Id: I6c70a52c68fdcdbf211217d30c96e1c2877c7f90
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2009
Tested-by: build bot (Jenkins)
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Instead of adding regparm(0) to each assembler function called
by coreboot, add an asmlinkage macro (like the Linux kernel does)
that can be different per architecture (and that is empty on ARM
right now)
Change-Id: I7ad10c463f6c552f1201f77ae24ed354ac48e2d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1973
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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It only has two files, move them to src/lib
Change-Id: I17943db4c455aa3a934db1cf56e56e89c009679f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1959
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: If8bce4ebde9101ac9087fcbd43adc0e08c26352d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/1957
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Set_boot_successful depends on CMOS parts that non-PC80
platforms do not have. For now, make the current path
depend on CONFIG_PC80_SYSTEM, and make the alternative
empty.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I68cf63367c8054d09a7a22303e7c04fb35ad0153
Reviewed-on: http://review.coreboot.org/1954
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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Change-Id: Ia0bbd3bec6588219ce24951c0bcebefc6b6ec80e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1940
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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The use of ramstage.a required the build system to handle some
object files in a special way, which were put in the drivers
class.
These object files didn't provide any symbols that were used
directly (but only via linker magic), and so the linker never
considered them for inclusion.
With ramstage.a gone, we can drop this special class, too.
Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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We moved GNVS to it's own section, but forgot to tell the cbmem code
about it. This is purely cosmetical, but add it anyways.
Change-Id: Icb3788c0325ea79cc1efff4a876412d07da7936e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1782
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Several small improvements of the stack checking code:
- move the CPU0 stack check right before jumping to the payload
and out of hardwaremain (that file is too crowded anyways)
- fix prototype in lib.h
- print size of used stack
- use checkstack function both on CPU0 and CPU1-x
- print amount of stack used per core
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Test: Boot coreboot on Link, see the following output:
...
CPU1: stack: 00156000 - 00157000, lowest used address 00156c68,
stack used: 920 bytes
CPU2: stack: 00155000 - 00156000, lowest used address 00155c68,
stack used: 920 bytes
CPU3: stack: 00154000 - 00155000, lowest used address 00154c68,
stack used: 920 bytes
...
Jumping to boot code at 1110008
CPU0: stack: 00157000 - 00158000, lowest used address 00157af8,
stack used: 1288 bytes
Change-Id: I7b83eeee0186559a0a62daa12e3f7782990fd2df
Reviewed-on: http://review.coreboot.org/1787
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In hardwaremain() we can't add timestamps before we actually
reinitialized the cbmem area. Hence we kept the timestamps in
an array and added them later. This is ugly and intrusive and
helped hiding a bug that prevented any timestamps to be logged
in hardwaremain() when coming out of an S3 resume.
The problem is solved by moving the logic to keep a few timestamps
around into the timestamp code. This also gets rid of a lot of ugly
ifdefs in hardwaremain.c
Change-Id: I945fc4c77e990f620c18cbd054ccd87e746706ef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1785
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Some usb debug devices don't respond fast enough. The linux kernel
(which uses almost the same usbdebug code) added a bit more
retry code, so let's copy that. Even if it might look stupid,
i pass the DBG_LOOPS argument through all functions to keep
the code at least a bit in sync with the linux kernel code.
Change-Id: I7c4b63b8bf1d2270fd6b8c8aa835e2cb324820bd
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1375
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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EHCI debug allows to send message with 8 bytes length, but
we're only sending one byte in each transaction. Buffer up
to 8 bytes to speed up debug output.
Change-Id: I9dbb406833c4966c3afbd610e1b13a8fa3d62f39
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1357
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
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This is used by the SPI driver and ELOG.
It requires SMM TSEG and a _heap/_eheap region defined in the
linker script. The first time malloc is called in SMM the
start and end pointers to the heap region will be relocated
for the TSEG region.
Enable SPI flash and ELOG in SMM and successfully
allocate memory. The allocated addresses are verified
to be sure they are within the TSEG heap region:
smm.elf:00014000 B _eheap
smm.elf:00010000 B _heap
TSEG base is 0xad000000
Memory allocated in ELOG:
ELOG: MEM @0xad018030
Change-Id: I5cca38e4888d597cbbfcd9983cd6a7ae3600c2a3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1312
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Previous patches implemented stack overflow checking for the APs.
This patch builds on the BSP stack poisoning patch to implement
stack overflow checking for the BSP, and also prints out maximum
stack usage. It reveals that our 32K stack is ridiculously oversized,
especially now that the lzma decoder doesn't use a giant 16K on-stack
array.
Break the stack checking out into a separate function, which
we will later use for the APs.
CPU0: stack from 00180000 to 00188000:Lowest stack address 00187ad8
To test failure, change the DEADBEEF stack poison value in c_start.S
to something else. Then we should get an error like this:
Stack overrun on BSP.Increase stack from current 32768 bytes
CPU0: stack from 00180000 to 00188000:Lowest stack address 00180000
Separate the act of loading from the act of starting the payload. This
allows us better error management and reporting of stack use. Now we
see:
CPU0: stack from 00180000 to 00188000:Lowest stack address 00187ad8
Tested for both success and failure on Link. At the same time, feel free
to carefully check my manipulation of _estack.
Change-Id: Ibb09738b15ec6a5510ac81e45dd82756bfa5aac2
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/1286
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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We accomplish this goal by getting rid of the huge auto array in the
ram stage. This will in turn let us reduce CONFIG_STACK_SIZE.
We have to leave it on the stack in CAR as that's the simple way to
keep it private. It does not matter then as there is only one core
that is active.
Change-Id: Ie37a057ccae088b7f3bb4aab6de2713e64d96df6
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/1271
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Since coreboot is running very short, we don't free memory.
Hence, drop (dummy) free()
Change-Id: I6e2737f07c6b9f73ebfad7d124b97a57cb7454a3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1274
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This check got in the code when some Linux distros shipped broken linkers
around 1999.
Since then, the code around that check was changed, and it does not make
sense anymore to have this check.
Change-Id: I37c6b690d72f55c18ba4c34e8541a6a441e5e67a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1275
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Brevity is the soul of wit, except for error messages;
then it's a sign of witlessness. I can say this because
this error message may be my fault, although it is lost
in the 20th century code base so who knows.
Anyway, when memalign dies, it's not a bad idea to have
a lot of information about what went wrong. So instead
of the terse single bit of "something failed" this patch
changes things to be a bit more useful.
Change-Id: I8851502297e0ae9773912839ebfdf4f9574c8087
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/1270
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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If serial uart (8250/16x50) takes abnormally long to respond, give
up on logging to serial console and instead let the system boot.
Also reference bit in LSR register with correct name.
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Ported from 9dd3ef165a1bf1bc404056d3e54337de1a15ac90 to
uart8250mem.c:
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Iaca4f57389c887110e6406d45053935891c96838
Reviewed-on: http://review.coreboot.org/826
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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- Prefix all CBFS output messages with CBFS:
- Add an option DEBUG_CBFS that is off by default. Without DEBUG_CBFS
enabled, the code will no longer print all the files it walks for
every file lookup.
- Add DEBUG() macro next to LOG() and ERROR() to specify which messages
should only be visible with DEBUG_CBFS printed.
- Actually print a message when the file we're looking for was found. :)
old:
Searching for fallback/coreboot_ram
Check cmos_layout.bin
Check pci8086,0106.rom
Check fallback/romstage
Check fallback/coreboot_ram
Change-Id: I2d731fae17a5f6ca51d435cfb7a58d6e017efa24
Stage: loading fallback/coreboot_ram @ 0x100000 (540672 bytes), entry @ 0x100000
Stage: done loading.
new:
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (507904 bytes), entry @ 0x100000
CBFS: stage loaded.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/993
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Sandybridge memory initialization produces some amount of training data
that has to be kept around in CBMEM. Add a descriptive name to the CBMEM
pretty printer to prevent it from just printing the hex value.
Change-Id: I587c0bc3dfcf389ba298d445d2594eef73bc69a8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/990
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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1. Move the Stack to high memory.
2. Restore the MTRR before Coreboot jump to the wakeup vector.
Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/623
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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Add a memalign function and have malloc use it. Also,
change the default alignment for malloc to u64-aligned.
Change-Id: I0788637008f5cb5ac801d8bbdc430ca992c98e81
Signed-off-by: Ron Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/887
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
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... and always include IP checksumming in romstage.
It's generally useful and our upcoming port needs it.
Change-Id: I248402d96a23e58354744e053b9d5cca6b74ad3a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/827
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: Ia118ebe0a4b59bdcefd78895141a365170f6aed2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/737
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/736
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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The cbmem console structure and car global data are put in their own section,
with the cbmem console coming after the global data. These areas are linked
to be where CAR is available and at the very bottom of the stack.
There is one shortcoming of this change:
The section created by this change needs to be stripped out by the Makefile
since leaving it in confuses cbfstool when it installs the stage in the image.
I would like to make the tools link those symbols at the right location but
leave allocation of that space out of the ELF.
Change-Id: Iccfb99b128d59c5b7d6164796d21ba46d2a674e0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The appropriate Makefiles are modified to include the required
source code in compilation.
Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/722
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Add CBMEM type for the console buffer section.
Change-Id: I02757c06d71e46af77b02b90b0e6018a37b62406
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/720
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The CBMEM console driver saves console output in a CBMEM area, which
then is made available to Linux applications for perusing.
There are some system limitations which need to be worked around
to achieve this goal:
- some console traffic is generated before DRAM is initialized,
leave alone CBMEM initialized.
- after the RAM based stage starts, a lot of traffic is generated
before CBMEM is initialized.
As a result, the console log lives in three different places -
the bottom of the cache as RAM space, the CBMEM buffer (where it
is expected to be) and a static buffer used early in the RAM
stage.
When execution starts (in the cache as RAM mode), the console
buffer is allocated at the bottom of the cache as RAM memory
address range. Once DRAM is initialized, the CBMEM structure is
initialized, and then the console buffer contents are copied from
the bottom of the cache as RAM space into the CBMEM area right
before the cache as RAM mode is disabled. The
src/lib/cbmem_console.c:cbmemc_reinit() takes care of the
copying.
At this point the cache as RAM memory is about to be disabled,
but the ROM stage is still going generating console output. To
make sure this output is not lost, cbmemc_reinit() saves the new
buffer address at a fixed location (0x600 was chosen for this),
and the actual "printing" function checks to see if the RAM is
already initialized (the stack is in RAM), and if so, gets the
console buffer pointer from this location instead of using the
cache as RAM address.
When the RAM stage starts, a static buffer is used to store the
console output, as the CBMEM buffer location is not known. Then,
when CBMEM is reinitialized, cbmemc_reinit() again takes care of
the copying.
In case the allocated buffers are not large enough, the excessive
data is dropped, and the copying routine adds some text to the
output buffer to indicate that there has been data lost and how
many characters were dropped.
Change-Id: I8c126e31db6cb2141f7f4f97c5047f39a8db44fc
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/719
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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acpi_slp_type is defined in arch/acpi.h, so let's use that instead
of manually spreading extern u8 acpi_slp_type throughout the code.
Change-Id: Ia5eb420364c15ab5a764bc328bbd201ca9cb7837
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/714
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This patch adds code to initialize the time stamp collection
facility in coreboot. It adds a table in the CBMEM section, which
provides the base timer reading value (all other readings are
offsets of this one) and an array of timestamp id/timestamp value
pairs.
Just two values are being added now, this will have to be used
more extensively and also integrated into payloads to provide more
comprehensive boot process time measurements.
Also, since the CBMEM area could already contain a section (from the
previous run, before reset), when processing a section addition
request we should check if a section already exists and return its
address, if so.
Change-Id: I7ed9f5c400bc5432f228348b41fd19a67c36d533
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/713
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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We want to be able to share data between different phases of firmware
(rom stage/ram stage/payload). Coreboot CBMEM seems an appropriate
location for this data, but normally it is not initialized
until coreboot reaches the ram stage.
This change initializes the CBMEM while still in rom stage in
case CONFIG_EARLY_CBMEM_INIT is set.
Note that there is a discrepancy in how coreboot determines the
size of DRAM at rom and ram stages, get_top_of_ram() is used at
rom stage and is not defined for all platforms. Those platforms
will have to define this function should they enable the
CONFIG_EARLY_CBMEM_INIT flag.
Change-Id: I81691d45e28de59496fb227f2cca4e8c15ece717
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/711
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is developer's testtool. Output from a "rotate ones" -style
pattern helps figure out how DIMM addresses are encoded or routed
on a certain mainboard.
Scattered test should cover every data and address lines on the memory
bus, but is probably limited to the first bank of first DIMM.
Change-Id: I533a7a873bcc434f99e7faed9dc9337d9ab64196
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
[pg: rebase]
Reviewed-on: http://review.coreboot.org/294
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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