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2019-10-30Program loading: Handoff cbmem_top via calling argumentsArthur Heymans
There are a lot of different implementations to pass information from romstage to ramstage. These could all be unified by passing this information via cbmem. Often however these methods exist for that very purpose. This solves this by passing cbmem_top via the programs arguments. Change-Id: Id2031f7bb81ce65fc318313c270eb1fbae3b2114 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36272 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28lib/cbfs: Don't load XIP stages from bootblockArthur Heymans
This should improve boot times as it skips unnecessary read and writes. Change-Id: I8cf36613903783e741b2e3bfeeee5bc29ab26d5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-28lib/prog_loaders.c: Add prog_locate_hook()Frans Hendriks
There is no posibility to prevent loading images from cbfs at this stage For security features prog_locate_hook() is added. This hook can be used to prevent loading the image. BUG=N/A TEST=Created verified binary and verify logging on Facebook FBG-1701 Change-Id: I12207fc8f2e9ca45d048cf8c8d9c057f53e5c2c7 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-27src/[arch-lib]: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibb7b48a7a144421aff29acbb7ac30968ae5fe5ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/36329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27src: Use 'include <boot/coreboot_tables.h>' when appropriateElyes HAOUAS
Change-Id: I3d90e46ed391ce323436750c866a0afc3879e2e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36359 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-27fmap: Add get_fmap_flash_offset()Furquan Shaikh
CB:35377 changed the behavior of find_fmap_directory() to return pointer to CBMEM_ID_FMAP if fmap is cached in cbmem. lb_boot_media_params() calls find_fmap_directory to add offset of fmap in flash to coreboot table. However, because of the change in behavior of find_fmap_directory(), it ended up adding 0 as the offset. This change adds a new function get_fmap_flash_offset() which returns the offset of fmap in flash. Ideally, all payloads should move to using the FMAP from CBMEM. However, in order to maintain compatibility with payloads which are not updated, ensure that fmap_offset is updated correctly. Since find_fmap_directory() is no longer used outside fmap.c, this change also removes it from fmap.h and limits scope to fmap.c. In a follow up patch, we need to push a change to libpayload to expose the fmap cache pointer to lib_sysinfo. BUG=b:141723751 Change-Id: I7ff6e8199143d1a992a83d7de1e3b44813b733f4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-09-27lib/bootsplash: Fix compilationPatrick Rudolph
Add missing include. Tested on Supermicro X11SSH-TF. Change-Id: Id0c80ac646001a497e96cae4d48a0f09762eb936 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35613 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-23lib/fmap: Cache FMAP in cbmemPatrick Rudolph
For platform independend exposure of FMAP through a kernel module cache the FMAP in CBMEM. In addition add a pointer in coreboot tables pointing to the introduced CBMEM area. To not waste the allocated DRAM, use the cached CBMEM in RAM enabled stages if possible. Tested on qemu using https://github.com/9elements/linux/commits/google_firmware_fmap2 Tested on QEMU and Supermicro X11SSH-TF. Change-Id: I4e01c573c3edfa34dbba5fe7604d4f6e18b584d5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-15lib/coreboot_table: Show splashscreen in lb_table_initJohanna Schander
Every vga init implementation needs to cache the framebuffer state to be able to fill the lb_framebuffer struct later on in the fill_lb_framebuffer call. Showing the bootsplash afterwards guarantees to have the same interface into all the vga drivers. This is by far from ideal, as it only allows for a single driver at compile-time and should be adapted in the future. It was tested on the wip razer blade stealth using vgabios @ 1280x1024 and also in Qemu @ 1280x1024. By default the qemu framebuffer will be initialized in 800x600@32. This can be overwriten by configuration by setting CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_{X,Y}RES . Change-Id: I4bec06d22423627e8f429c4b47e0dc9920f1464e Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-14src/: Replace some __PRE_RAM__ useKyösti Mälkki
Change-Id: Iaa56e7b98aad33eeb876edd7465c56c80fd1ac18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-14arch/x86: Remove acpi_fail_wakeup() and cbmem_fail_resume()Kyösti Mälkki
Unused since commit d46b8d5. Change-Id: If0f1e0381dd7698f842dc1288ff222a4d5d4783c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35389 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13timestamps: Remove TIMESTAMP_CACHE_IN_BSSKyösti Mälkki
This was implemented for LATE_CBMEM_INIT support which has already been deprecated. Change-Id: I39225ba675bc3389e051e15b400a905431969715 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35375 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13timestamps: Further simplify timestamp_reinit()Kyösti Mälkki
Allocation of new table always happens in romstage. Change-Id: I089a84b372893fb3018a796fb1e16cd58753bdf4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35374 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12timestamps: Mostly remove struct timestamp_cacheKyösti Mälkki
Change-Id: Ifcd75630e562af302312f93bdf180aa90f18d21d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35290 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12timestamps: Refactor CBMEM hookKyösti Mälkki
Separate timestamp_sync_cache_to_cbmem() as it is only used with ENV_ROMSTAGE. Change-Id: Ibe18a5ecf09b2b87d8ee3e828728ad6a8a262206 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35280 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11timestamps: Improve collection for ENV_ROMSTAGE_OR_BEFOREKyösti Mälkki
Keep track of the active timestamp table location using a CAR_GLOBAL variable. Done this way, the entire table can be located outside _car_relocatable_data and we only switch the pointer to CBMEM and copy the data before CAR gets torn down. Fix comments about requirements of timestamp_init() usage. Remove timestamp_cache from postcar and ramstage, as CBMEM is available early on. Change-Id: I87370f62db23318069b6fd56ba0d1171d619cb8a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35032 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0Kyösti Mälkki
These platforms return to romstage from FSP only after already having torn CAR down. A copy of the entire CAR region is available and discoverable via HOB. Previously, CBMEM console detected on-the-fly that CAR migration had happened and relocated cbmem_console_p accoringlin with car_sync_var(). However, if the CAR_GLOBAL pointing to another object inside CAR is a relative offset instead, we have a more generic solution that can be used with timestamps code as well. Change-Id: Ica877b47e68d56189e9d998b5630019d4328a419 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35140 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09lib/spd_bin: Extend DDR4 spd informationEric Lai
From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-26arch/x86: Simplify <arch/early_variables.h>Kyösti Mälkki
This enables the use of .bss section for ENV_BOOTBLOCK and ENV_VERSTAGE even with CAR_GLOBAL_MIGRATION=y. In practice, boards with CAR_GLOBAL_MIGRATION=y currently build with romcc-bootblock so they will not be using .bss. Change-Id: Ie9dc14f3e528d3e4f48304f4d7de50df448a8af6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26lib/bootblock: Add simplified entry with basetimeKyösti Mälkki
This allows for minor optimization as num_timestamps becomes a constant zero for a function with local scope. The loop with calls to timestamp_add() gets removed from bootblock. Change-Id: Id230075c0e76fe377b6ea8c8ddf8318e07d29b91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26Split MAYBE_STATIC to _BSS and _NONZERO variantsKyösti Mälkki
These are required to cover the absensce of .data and .bss sections in some programs, most notably ARCH_X86 in execute-in-place with cache-as-ram. Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26Move and rename ARCH_STAGE_HAS_xxx_SECTION rulesKyösti Mälkki
Currently only x86 requires special handling here, for simplicity avoid introducing <arch/rules.h> and deal with this directly in <rules.h>. For consistency prefixes are changed from ARCH_ to ENV_. Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26lib: ramdetect: Register exception handlers for ARMv8Asami Doi
Register exception handlers to avoid a Synchronous External Abort that is raised when you try to access a non-memory address on ARMv8. An exception handler can jump over the faulting instruction. This is the feature only for QEMU/AArch64. Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Change-Id: I09a306ca307ba4027d9758c3debc2e7c844c66b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-08-23lib: hardwaremain: Call exception_init() as soon as possibleAsami Doi
Call exception_init() before calling cbmem_initialize() because ARMv8 on QEMU uses an exception handler to detect a ram size. Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Change-Id: If010234a6576414e7e174c075b599a4aa4c19eab Reviewed-on: https://review.coreboot.org/c/coreboot/+/35022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-22ACPI S3: Depend on RELOCATABLE_RAMSTAGEKyösti Mälkki
With RELOCATABLE_RAMSTAGE, S3 resume path only uses memory that is reserved from OS. So there is no need for low memory backup and recovery. Change-Id: If7f83711685ac445abf4cd1aa6b66c3391e0e554 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-21lib/bootsplash: Log bootsplash dimensions and framebuffer dimensionsJohanna Schander
The bootsplash.jpg needs to match the framebuffer resolution. Configuration errors are more visible if they can be compared easily. Changed message to be always printed: "Setting up bootsplash in ${FRAMEBUFFER_RESOLUTION}" Added message: "Bootsplash image resolution: ${IMAGE_RESOLUTION}" Change-Id: Ib4a06d53c0134b99d3e9e6d3eda9fa30fca9ef7d Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34598 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15lib: edid: Move manufacturer name from private extra to public infoHung-Te Lin
When debugging usually we want to print out a full identifier for panel, that should be manufacturer and part number. Previously the edid only contains ascii_string (which is usually the part number) but we should export manufacturer name as well. Change-Id: I0020fdd5b9f9331b25825876e0de4dc7e26b0464 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-11arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki
It is easier to track CAR_GLOBAL_MIGRATION which is the approach to be deprecated with the next release. This change enforces new policy; POSTCAR_STAGE=y is not allowed together with CAR_GLOBAL_MIGRATION=y. Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-10include, lib: Add <inttypes.h> printf macrosJacob Garber
In general, third party code (such as vboot) doesn't know what the underlying types are for the integers in <stdint.h>, so these macros are useful for portably printing them. Of these definitions, coreboot so far has only used PRIu64 (in one place), which isn't needed anymore since we know what the underlying type of a u64 is. Change-Id: I9e3a300f9b1c38e4831b030ff8af3fed2fa60f14 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-10src: Include <stdint.h> instead of <inttypes.h>Jacob Garber
The <inttypes.h> header currently does nothing but include the definitions from <stdint.h>, so let's #include that directly instead. Change-Id: I9d83ad37d0d7300a093001596ce3f0b3830c5701 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-10string: implement strspn, strcspn, atolYuji Sasaki
Change-Id: Id8fa880357124b620bde8884949bd8ffff7d0762 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-08lib/stage_cache: Refactor Kconfig optionsKyösti Mälkki
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE. Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache. There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE. As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option. Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-08lib/edid: Add suport for display rotationNicolas Boichat
Sometimes the display native orientation does not match the device default orientation. We add a parameter to be passed to libpayload, which can then do the rotation. BUG=b:132049716 TEST=Boot krane, see that FW screen is orientation properly. Change-Id: I5e1d94b973a3f615b73eebe0ca1202ba03731844 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-06lib: Throw an error when ramdisk is present but initrd.size is 0Asami Doi
It fails if you call extract() when ramdisk is present but initrd size is 0. This CL adds if-statement to throw an error when initrd size is 0. Change-Id: I85aa33d2c2846b6b3a58df834dda18c47433257d Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-31lib/bootmem: Prepare for OpenSBIPatrick Rudolph
Add a new bootmem memory type OpenSBI. It's similar to BL31 on aarch64. Required for OpenSBI integration. Change-Id: I5ceafd5a295f4284e99e12f7ea2aa4c6d1dbb188 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-29Revert "src/security/vboot: Add option to skip display init with vboot 2.0"Christian Walter
This reverts commit 598af2e2c2785c00eb4290cdcefe1082b2a6f858. Reason for revert: This commit breaks every board with VBOOT enabled if the platform is apollolake, broadwell, skylake, baswell, baytrails or icelake. The reason is, that the SoC selects VBOOT_MUST_REQUEST_DISPLAY by default, and this has a dependency now on VBOOT_MAY_SKIP_DISPLAY_INIT. This will only be auto-selected if it is a CHROMEOS platform. Change-Id: I3872d9aa993326ded135d8a5d950d5b1b1eddf34 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34308 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-28lib: Rewrite qemu-armv7 ramdetectPatrick Rudolph
* Move armv7 RAM dection to a common place * Enable it for all emulated platforms * Use 32bit probe values and restore memory even on failure * Use the new logic on the following boards: ** qemu-armv7 ** qemu-riscv Tested on qemu-system-riscv: Fixes kernel panic due to wrong memory limits reported. Change-Id: I37386c6a95bfc3b7b25aeae32c6e14cff9913513 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-26lib: add string.c to verstagePatrick Georgi
Change-Id: I5aa3bb2c72dcf127d418c989f6b63c9b1f412f08 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-26src/device/oprom: Fix bootsplash display code for optionromsJohanna Schander
So far the bootsplash is only correctly rendered if the framebuffer is set up as 1024x768@16. Different resolutions did not show anything, differnent depth resulted in the distorted images. This commit removes this limit by using the actual framebuffer resolutions and combines the code for x86 and yabel. For the moment the bootsplash is still limited to VGA-OptionROM framebuffer init. It was tested in 1280x1024@32 on the wip razer blade stealth using the intel vgabios. Change-Id: I5ab7b8a0f28badaa16e25dbe807158870d06e26a Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34537 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23vboot: deprecate vboot_handoff structureJoel Kitching
vboot_handoff is no longer used in coreboot, and is not needed in CBMEM or cbtable. BUG=b:124141368, b:124192753 TEST=make clean && make runtests BRANCH=none Change-Id: I782d53f969dc9ae2775e3060371d06e7bf8e1af6 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33536 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23src/lib/hexdump: Use size_t for indicesElyes HAOUAS
Spotted out using -Wconversion gcc warning option. Change-Id: I29a7ae8c499bb1e8ab7c8741b2dfb7663d82a362 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-19src: Make implicit fall throughs explicitJacob Garber
Implicit fall throughs are a perpetual source of bugs and Coverity Scan issues, so let's squash them once and for all. GCC can flag implicit fall throughs using the -Wimplicit-fallthrough warning, and this should ensure no more enter the code base. However, many fall throughs are intentional, and we can use the following comment style to have GCC suppress the warning. switch (x) { case 1: y += 1; /* fall through */ case 2: y += 2; /* fall through - but this time with an explanation */ default: y += 3; } This patch adds comments for all remaining intentional fall throughs, and tweaks some existing fall through comments to fit the syntax that GCC expects. Change-Id: I1d75637a434a955a58d166ad203e49620d7395ed Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-17lib: Remove the BOOTBLOCK_CUSTOM compile guardAsami Doi
This CL allows that everyone can use main() in lib/bootblock.c even if you select CONFIG_BOOTBLOCK_CUSTOM. I also rename main functions used in some soc/ to avoid the collision with the main function defined at lib/bootblock.c. Change-Id: I0575c9d1ce9dea9facfcc86760dff4deee9c1e29 Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34250 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-15lib/bootmode: Include 'vboot/misc.h'Elyes HAOUAS
Don't include unneeded 'vendorcode/google/chromeos/chromeos.h', when only 'vboot/misc.h' is used. Change-Id: I99484c29e5a3e13f1fea277f13c2f08a8a46bd88 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Joel Kitching <kitching@google.com>
2019-07-15src: Use '#include <timestamp.h>' when neededElyes HAOUAS
Change-Id: Ic0483982e8115ae99367d08d8ed77b8a316f5405 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-13fit_payload: Always set DT sizeJulius Werner
CB:32870 changed FIT loading code to make an FDT mandatory (because the platforms that can use FIT images always need an FDT). Remove one left-over conditional that is now dead code. Found by Coverity. Change-Id: Ia7765d45f068ab4bdc720ea7ae87dcc62a4b7d3d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-09arch/x86: Replace some uses of SMM_TSEGKyösti Mälkki
No reason why the files could not be used with ASEG. Attempts to use malloc() from ASEG would still fail, though, due the lack of heap. Change-Id: Idf470ae84eb34c442e833925510b08d5314e7638 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34126 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07lib/romstage_stack.c: Remove fileKyösti Mälkki
After platforms have moved to POSTCAR_STAGE=y the only remaining user is binaryPI now. Make it simpler. Change-Id: Ia70c5c85e06c42f965fb7204b633db9b619e2e84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-07src/security/vboot: Add option to skip display init with vboot 2.0Sukerkar, Amol N
This config option, when set, will allow the platform to skip display initialization in normal (non-developer, non-recovery) mode. This allows platforms that do not implement firmware UI in normal mode to skip the display init in firmware. TEST=Set option CONFIG_VBOOT and clear CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display should initialize in ramstage when platform boots. Set CONFIG_VBOOT and set CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display initialization should be skipped in coreboot. Signed-off-by: Sukerkar, Amol N <amol.n.sukerkar@intel.com> Change-Id: Icadad6da34dcb817af02868e89a94ea62dbfa7b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-04lib/romstage_stack.c: Remove unused functionsArthur Heymans
Change-Id: I1e66ff3fe7462dfeae2a7ce7e3a8083cf90a15f9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33936 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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