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2018-02-07lib/stage_cache: Add save/get raw storageMarshall Dawson
Leverage the stage_cache mechanism to store a non-specific type of data. This is not interesting when the location for the cache is in cbmem. However it will be more useful when an external location is used, e.g. when the cache is in TSEG, locked from user modification. Change-Id: Iaf0b25ebe14c176bbd24fc8942f902f627ca8e6f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-01lib/stage_cache: Add debug messages for failuresMarshall Dawson
Communicate additional status to the console when the save and load functions do not function as expected. The most likely scenario for an error is when using a cache that is external to cbmem, and restricted in size. Change-Id: Ic9a709c11152b3b9cb40abfc204151f9636b5a4c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-25lib: include timer.c for all stages for GENERIC_UDELAYAaron Durbin
In order to fully utilize GENERIC_UDELAY in smm and postcar the udelay() implementation needs to be included. Do that. BUG=b:72378235,b:72170796 Change-Id: Ia20c1ed41ee439bb079e00fb7bd9c1855e31e349 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07boardid: Add helpers to read sku_id strapping into coreboot tablesJulius Werner
On many recent Chrome OS boards, the desire to unite more configurations under the same image has led to the need of a "SKU ID" that identifies different configurations of the same board (e.g. with certain optional components stuffed or not stuffed, or replaced with a comparable component). This is markedly different from the existing "board ID", because that is reserved to count "revisions" -- changes made to the same configuration over time during the development process. This patch adds support to have a mainboard define this SKU ID and pass it through the coreboot table like we already have for board IDs. Change-Id: I8aabffe8e1003b0d6fb70d689ae513ca4b46aeda Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22696 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Switch from Kconfig to weak functionsJulius Werner
This patch switches the board_id and ram_code helper framework to use weak functions rather than Kconfigs to determine whether the board supplies these IDs. This cuts down on the amount of boilerplate Kconfigs many boards have to set and also gives them more flexibility, such as being able to determine at runtime whether a given ID is present. Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22695 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Minor clean up and standardizationJulius Werner
Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-06Kconfig: Remove BOARD_ID_MANUAL optionJulius Werner
The BOARD_ID_MANUAL and BOARD_ID_STRING options were introduced for the Urara board which is now long dead, and have never been used anywhere else. They were trying to do something that we usually handle with a separate SKU ID these days, whereas BOARD_ID is supposed to be reserved for different revisions of the same board/SKU. Get rid of it to make further refactoring of other options easier. Also shove some stuff back into the Urara mainboard that should've never crept into generic headers. Change-Id: I4e7018066eadb38bced96d8eca2ffd4f0dd17110 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07src: Fix all Siemens copyrightsMario Scheithauer
Some Siemens copyright entries incorrectly contain a dot at the end of the line. This is fixed with this patch. Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07lib/ramtest: Add commentPatrick Rudolph
Add a comment about the tested RAM region size. Change-Id: I29e99a06777bd21a65aa67049ceede4fd8adb603 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maximilian Schander <coreboot@mimoja.de> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-03lib/reg_script.c: Remove unused assignmentPaul Menzel
Fix the warning below. ``` CC bootblock/lib/reg_script.o src/lib/reg_script.c:375:11: warning: Value stored to 'value' during its \ initialization is never read uint64_t value = msr.hi; ^~~~~ ~~~~~~ ``` Found-by: Clang static analyzer scan-build (clang version 4.0.1-6 (tags/RELEASE_401/final)) Fixes: fd461e39 (regscript: Add support for MSR type) Change-Id: I218e45d12f2f00e2ad4cfe5410029f407b57568d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-31intel/common/smbus: increase spd read performanceKane Chen
This change increases the spd read performance by using smbus word access. BUG=b:67021853 TEST=boot to os and find 80~100 ms boot time improvement on one dimm Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/22072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-28lib: Prepare for libhwbase' generated config fileNico Huber
Add new libhwbase options and add a class for files generated during build. This follows the same pattern as for libgfxinit. Change-Id: Ie5b84992fa687e4e94b6d959a64086c638f66eb8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-20lib/gpio: constify array inputsAaron Durbin
The arrays of gpio_t are not manipulated in any way within the gpio library. Add const to indicate that. Change-Id: Ie32ab9de967ece22317e2b97b62e85b0757b910d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-16drivers/elog: Fix debug build errorsJohn E. Kabat Jr
Add hexdump.c to Makefile.inc and change an elog_debug format to use %z for size_t arguments. This corrects build errors when ELOG_DEBUG is used. Change-Id: I3d5547eed8ada7c4bdcbbb8bb9d6965ade73beda Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com> Reviewed-on: https://review.coreboot.org/21769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-28Kconfig: Move libhwbase related options into lib/KconfigNico Huber
More will follow so better move them where they are used. Also remove defaults and add dependencies to not clutter .config files up that don't have any of these options selected. Change-Id: I3a255c821cc26aeb66e4fd6adf7142d7e856f5ac Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-26Use stopwatch_wait_until_expired where applicableJonathan Neuschäfer
Change-Id: I4d6c6810b91294a7e401a4a1a446218c04c98e55 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-09-26src/lib/Makefile.inc: Remove loaders subdirectoryJonathan Neuschäfer
src/lib/loaders was removed in commit 899d13d0df ("cbfs: new API and better program loading"). Change-Id: Ic7a9f5d83c5f9445bf24970e0c8cc645dd1944ff Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-23toolchain: Always use GCC for Ada sourcesNico Huber
We can't use $(CC) in case it's set to Clang. TEST=Built one target with Ada sources before and after this change and verified that the same compiler commands are emitted. Change-Id: I9b8ea35352d74b364f09fc12d8d981ca42f8b7c8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-23toolchain: Use xcompile proposed CFLAGS for AdaNico Huber
We don't output special ADAFLAGS in xcompile but its CFLAGS are compatible with and necessary for Ada too. So use the latter and make sure we use them for libgnat too. Fixes i386 builds with x86_64 toolchain. TEST=Gave libgfxinit a shot on lenovo/t420. Change-Id: I0d13f182acfaa9bd1b608edd8a508c4ceedef3b3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-21src/lib/ubsan: Indent macros to improve readabilityJonathan Neuschäfer
Change-Id: Ide4e58e584a1a2bbc1b861e2c4dd943a1aeb35ab Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-14timestamp: Add function to get time since bootWerner Zeh
Add a function to retrieve the elapsed time since boot. For that purpose use the base time in the timestamp table among with the current timestamp at call time of the function. So more precise the returned time is the elapsed time since the timestamp was initialized scaled in microseconds. This was chosen to get a reliable value even on platforms where the TSC might not be reset on software reset or warm start. Change-Id: Ib93ad89078645c0ebe256048cb48f9622c90451f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08stage_cache: Add rmodule params in metadataKyösti Mälkki
The change allows to update rmodule parameters after it has been loaded from stage cache. Change-Id: Ib825ffe245d447ad3a8246f7dbd52c6e34103a0c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-06postcar: Add cbmem_stage_cacheKyösti Mälkki
S3 resume path executing through postcar was unable to utilise cached ramstage in CBMEM. Change-Id: Icc8947c701ca32b4f261ebb78dfc1215b7ed2da0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04lib/cbmem: provide optional cbmem top initialization hookAaron Durbin
Provide a hook to allow an optional one-time cbmem_top() initialization. The new function, cbmem_top_init(), is called on the first expected initialization of cbmem based on the Kconfig options LATE_CBMEM_INIT and EARLY_CBMEM_INIT. Change-Id: I89edd2d11f226217c8e2aaca829b4f375a2cff28 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03lib/cbmem: use globals for non CAR global migration platformsAaron Durbin
For CAR platforms which don't migrate globals real globals can be directly used. This alleviates the need to peform partial recovery on every cbmem access which in turn acts like all non-CAR platforms or any stages which execute entirely out of RAM. Change-Id: I31c08dd6473324424d5d42fe6b56d42fe635929e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03lib/cbmem: remove cbmem_region_used()Aaron Durbin
The cbmem_region_used() function wasn't being utilized outside this module. Threfore, reduce the surface area. Change-Id: I28a9d02221048ab0aa4cd3d986d17ee7692ce636 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03lib/imd_cbmem: remove unused #includeAaron Durbin
Change-Id: I18a08faa5f9f5330cdb509c27a8ab7a3aa8e5b73 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03lib/imd_cbmem: remove unused funcitonAaron Durbin
The cbmem_fail_recovery() function was no longer used. I'm not sure why the compiler never complained. Regardless, delete it. Change-Id: I7d94118068064c61252d1b5ca9d8e92658a699e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-30lib/program.ld: Guard .id section placementNico Huber
For x86, we place the .id section at 4GiB - CONFIG_ID_SECTION_OFFSET. To take effect, we have to guard the conflicting default placement in `program.ld`. Also, as we only include the .id section into the boot- block, guard it by ENV_BOOTBLOCK too. Change-Id: Idc7cbd670ce4f75b7790ff8d95578683e355ba7e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20810 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-07-27timestamp: Apply factor to recorded stampsKyösti Mälkki
If we dont have a constant TSC rate, timestamp table has odd leaps and may appear to run backwards. Add functionality to apply a factor such that all stamps are in the same timebase. Change-Id: Idab9c2c00e117c4d247db8cc9a2897640fa01edd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-26Port cmos.default handling to C environment bootblockNico Huber
Gather related code in the new file drivers/pc80/rtc/mc146818rtc_boot.c, call sanitize_cmos() from C environment bootblock. Change-Id: Ia5c64de208a5986299c0508d0e11eeb8473deef1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25src/lib: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
Change-Id: I332c44c6db0a5ea05db076474caf77d6c50d4673 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24Fix files with multiple newlines at the end.Martin Roth
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20704 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-06src/lib: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Idcea3f8b1a4246cb6b29999a84a191a3133e5c78 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-29lib/spd_bin: Use proper I2C addressesNico Huber
Use the plain address instead of the weird shifted encoding (e.g. if we'd use `0xa0` as address, it's actually `0x50` encoded into a write command). Change-Id: I6febb2e04e1c6de4294dfa37bde16b147a80b7a8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27lib/coreboot_tables: Zero framebuffer structureDuncan Laurie
Zero the framebuffer structure so if it is not filled in (either if no display is present or if there is an error) then it does not provide garbage data to the payload. This was noticed when booting a board without a display attached as the payload wrote to the framebuffer at a random address. With this change the payload can properly handle the case where a display is not attached and not corrupt memory. Change-Id: I8114d88496cd2a4f2e7f07f377fe76f3180a7f40 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-06-21cr50: process uninitialized values gracefullyVadim Bendebury
The vboot code tries reading rollback protection indices from the TPM, and if the attempt to read returns TPM_E_BADINDEX, it decides that the TPM has not yet been initialized for the Chromebook use, and needs to be taken through the factory initialization sequence. TPM_E_BADINDEX is an internal representation of the TPM error 0x28b, generated on attempts to read a non existing NVMEM space. If the space exists, but has never been written the TPM returns error 0x14a. This condition (the space exists but not written) could happen if the previous factory initialization attempt was interrupted right after the space was created. Let's map this error to the same internal representation (TPM_E_BADINDEX) so that the Chrome OS device could recover when this condition occurs. BRANCH=reef, gru BUG=b:37443842 TEST=verified that the Pyro device stuck in TPM error state recovered when this patch was applied. Change-Id: I6ff976c839efcd23ae26cef3ee428e7ae02e68f8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/20299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-14Add support for Undefined Behavior SanitizerRyan Salsamendi
Initial support for undefined behavior sanitizer in ramstage. Enabling this will add -fsanitize=undefined to the compiler command line and link with ubsan.c in ramstage. Code with UB triggers a report with error, file, and line number, then aborts. Change-Id: Ib139a418db97b533f99fc59bcb1a71fb6dcd01d8 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-06-14cbmem_console: Fix undefined behaviorRyan Salsamendi
Fixes report found by undefined behavior sanitizer. Left shifting an int where the right operand is >= width of type is undefined. Add ul suffix since it's safe for unsigned types. Change-Id: I4b2365428e421085285006bc1ea8aea75890ff65 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-06-13Consolidate reset API, add generic reset_prepare mechanismJulius Werner
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-09lib/spd_bin: Print out correct SMBus SPD address in dump_spd_infoFurquan Shaikh
With change dd82edc388 (lib/spd_bin: make SMBus SPD addresses an input), SMBus SPD addresses are accepted from the mainboard and not calculated within the spd_bin library routines. Use the addr_map values to print correct address in dump_spd_info. Change-Id: Iff37e382aeac9704f74bafc2ecb27f14c478723f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-04lib/coreboot_tables: Remove weak fill_lb_framebuffer()Nico Huber
Remove the weak function stub fill_lb_framebuffer() and guard with the new `CONFIG_LINEAR_FRAMEBUFFER` instead. Change-Id: Ia9e477c2d501b249a632968b5636ac803323895a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-04Kconfig: Add choice of framebuffer modeNico Huber
Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for `HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model that with additional symbols. Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-30lib/edid: Split out fill_lb_framebuffer()Nico Huber
Place it into new edid_fill_fb.c, and invert the logic of the Kconfig guard (NATIVE_VGA_INIT_USE_EDID is now !NO_EDID_FILL_FB). It has to be selected by all drivers that use MAINBOARD_DO_NATIVE_VGA_INIT but pro- vide their own fill_lb_framebuffer() implementation. Change-Id: I90634b835bd8e2d150b1c714328a5b2774d891bd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-27lib/spd_bin: make SMBus SPD addresses an inputAaron Durbin
Instead of assuming the mapping of dimm number to SPD SMBus address, allow the mainboard to provide its own mapping. That way, global resources of empty SPD contents aren't wasted in order to address a dimm on a mainboard that doesn't meet the current assumption. Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2017-05-18cbmem_console: Improve 'cbmem -1' behavior for truncated pre-CBMEM logsJulius Werner
The 'cbmem -1' flag that cuts off console output before the last boot will ignore content from earlier stages if it was truncated due to lack of pre-CBMEM console space. This patch makes the "log truncated" message more specific and adds it as an additional cut-off marker to 'cbmem -1' to counteract that problem. Also raise the log level of the coreboot banner one step to BIOS_NOTICE to make it more likely to be included in the output for 'cbmem -1' to find. (I believe NOTICE is reasonable but I wouldn't want to go as far as WARN which should be reserved for actual problems. Of course this is not ideal, but then again, our whole log-level system really isn't... it would be better if we could make it always print a banner to the CBMEM console without affecting the UART at the same time, but that would require a larger amount of work.) Change-Id: I58288593dfa757e14f4a9da4ffa7e27b0b66feb9 Reported-by: https://ticket.coreboot.org/issues/117 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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