summaryrefslogtreecommitdiff
path: root/src/lib
AgeCommit message (Collapse)Author
2014-03-11rmodule: allow rmodule header structure to be used by userlandAaron Durbin
In order for userland to create rmodules the common code should be shareable. Therefore, convert the short u<width> name types to the posix uint<width>_t types. Additionally, move the definition of the header structure to a new rmodule-defs.h header file so that userland can include that without pulling in the coreboot state. Change-Id: I54acd3bfd8c207b9efd50a3b6d89efd5fcbfc1d9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5363 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-08lib/dynamic_cbmem.c: Include `cbmem_console.h`Paul Menzel
Broken with commit 1d7541fe (console: Fix includes). Change-Id: If41f9e08df98d79b7bbf740b1a5634d0140207be Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5351 Tested-by: build bot (Jenkins)
2014-03-07x86: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING optionAaron Durbin
Boot speeds can be sped up by mirroring the payload into main memory before doing the actual loading. Systems that would benefit from this are typically Intel ones whose SPI are memory mapped. Without the SPI being cached all accesses to the payload in SPI while being loaded result in uncacheable accesses. Instead take advantage of the on-board SPI controller which has an internal cache and prefetcher by copying 64-byte cachelines using 32-bit word copies. Change-Id: I4aac856b1b5130fa2d68a6c45a96cfeead472a52 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5305 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04Add a generic register script handlerDuncan Laurie
This is based on the RCBA configuration setup from haswell. It handles PCI, BARs, IO, MMIO, and baytrail-specific IOSF. I did not extend it to handle MSR yet but that would be another potential register type. There are a number of approaches to this kind of thing, but in the end they have a lot of switch statements and a mass of #defines. I'm not particularly set on any of the details so comments welcome. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Ib873936ecf20fc996a8feeb72b9d04ddb523211f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175206 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4923 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04usbdebug: Move Kconfig under drivers/usbKyösti Mälkki
This menu may become a bit more complicated with addition of new USB hardware so move it out of console/. Change-Id: Ieb330675b9227a3e53d093f7c2b5a65e3842dc82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5307 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04uart8250: Move under drivers/uartKyösti Mälkki
Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5236 Tested-by: build bot (Jenkins)
2014-03-04uart8250mem: Unify calls with generic UARTKyösti Mälkki
NOTE: UART base for SMM continues to be broken, as it does not use the address resource allocator has assigned. Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5235 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04uart8250io: Unify calls with generic UARTKyösti Mälkki
Change-Id: I6d56648e56f2177e1d5332497321e718df18300c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5234 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04console: Fix includesKyösti Mälkki
Do not pull in console hw-specific prototypes everywhere with console.h as those are not needed for higher levels. Move prototypes for UARTs next to other consoles. Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5232 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04uart8250: Fix and unify baudrate divisor calculationKyösti Mälkki
Divisor is a function of requested baudrate, platform-specific reference clock and amount of oversampling done on the UART reference. Calculate this parameter with divisor rounded to nearest integer. When building without option_table or when there is no entry for baud_rate, CONFIG_TTYS0_BAUD is used for default baudrate. For OxPCIe use of 4 MHz for reference was arbitrary giving correct divisor for 115200 but somewhat inaccurate for lower baudrates. Actual hardware is 62500000 with 16 times oversampling. FIXME: Field for baudrate in lb_tables is still incorrect. Change-Id: I68539738469af780fadd3392263dd9b3d5964d2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5229 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04uart: Do not guard entire include file by config optionsKyösti Mälkki
Do not guard the file by CONFIG_CONSOLE_SERIAL8250 or CONFIG_CONSOLE_SERIAL8250MEM or CONFIG_CONSOLE_SERIAL. Don't do indirect includes for <uart8250.h>. The config-specific options are already properly guarded, and there is no need to guard the register and bit definitions. Change-Id: I7528b18cdc62bc5c22486f037e14002838a2176e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4585 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-03lib/selfboot: s_srcaddr is uninitialized.Edward O'Callaghan
s_srcaddr is uninitialized in the BSS section, leading to a garbage valued operand on the LHS of a '<' on line 383. Change-Id: Ie4fec91b09c70fb1d91ad3918ac3f60653fa1d83 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5314 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-03coreboot: remove unused get_lb_mem() functionAaron Durbin
The get_lb_mem() is no longer used. Therefore, remove it. Change-Id: I2d8427c460cfbb2b7a9870dfd54f4a75738cfb88 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5304 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03selfboot: use bootmem infrastructureAaron Durbin
Instead of packing and unpacking entries in lb_mem use the bootmem infrastructure for performing sanity checks during payload loading. Change-Id: Ica2bee7ebb0f6bf9ded31deac8cb700aa387bc7a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5303 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03coreboot: introduce notion of bootmem for memory map at bootAaron Durbin
The write_coreboot_table() in coreboot_table.c was already using struct memrange for managing and building up the entries that eventually go into the lb_memory table. Abstract that concept out to a bootmem memory map. The bootmem concept can then be used as a basis for loading payloads, for example. Change-Id: I7edbbca6bbd0568f658fde39ca93b126cab88367 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5302 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03coreboot: introduce arch_payload_run()Aaron Durbin
The selfboot() function relied on global variables within the selfboot.c compilation unit. Now that the bounce buffer is a part of struct payload use a new architecture-specific arch_payload_run() function for jumping to the payload. selfboot() can then be removed. Change-Id: Icec74942e94599542148561b3311ce5096ac5ea5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5300 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03selfboot: store bounce buffer in struct payloadAaron Durbin
In order to break the dependency on selfboot for jumping to payload the bounce buffer location needs to be communicated. Therefore, add the bounce buffer to struct payload. Change-Id: I9d9396e5c5bfba7a63940227ee0bdce6cba39578 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5299 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03coreboot: use struct payload for selfload()Aaron Durbin
In order to encapsulate more data for self loading use struct payload as the type. That way modifications to what is needed for payload loading does not introduce more global variables. Change-Id: I5b8facd7881e397ca7de1c04cec747fc1dce2d5f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5298 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03coreboot: move common code to payload_run() from selfboot()Aaron Durbin
The selfboot() routine was perfoming most of the common teardown and stack checking infrastructure. Move that code into payload_run() to prepare removal of the selfboot() function. Change-Id: I29f2a5cfcc692f7a0fe2656cb1cda18158c49c6e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5297 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03coreboot: unify infrastructure for loading payloadsAaron Durbin
A payload can be loaded either from a vboot region or from cbfs. Provide a common place for choosing where the payload is loaded from. Additionally, place the logic in the 'loaders' directory similarly to the ramstage loader infrastructure. Change-Id: I6b0034ea5ebd04a3d058151819ac77a126a6bfe2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5296 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-25Kill ALT_CBFS_LOAD_PAYLOADVladimir Serbinenko
Not used anymore. Change-Id: Icf3a4a7f932776981048b805478582ad2b784182 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5132 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-25Remove CACHE_ROM.Vladimir Serbinenko
With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs depending on system configuration, hence screwing up I/O access and cache coherency in worst cases. CACHE_ROM requires the user to sanity check their boot output because the feature is brittle. The working configuration is dependent on I/O hole size, ram size, and chipset. Because of this the current implementation can leave a system configured in an inconsistent state leading to unexpected results such as poor performance and/or inconsistent cache-coherency Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5146 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-21lib/edid: Don't set vbe_valid in decode_edid.Vladimir Serbinenko
Decoding EDID doesn't yet mean that gfx mode is used. Change-Id: Icedd36f26877754f34dd59233cce72271d7f0b19 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5269 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-19printk: support and use %hh prefixPatrick Georgi
clang complains otherwise. Change-Id: I2ac98d7147ecd3d7064f17f8c9d214d44baedf97 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4717 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-02-16x86: provide infrastructure to backup default SMM regionAaron Durbin
Certain CPUs require the default SMM region to be backed up on resume after a suspend. The reason is that in order to relocate the SMM region the default SMM region has to be used. As coreboot is unaware of how that memory is used it needs to be backed up. Therefore provide a common method for doing this. Change-Id: I65fe1317dc0b2203cb29118564fdba995770ffea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5216 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-15coreboot: infrastructure for different ramstage loadersAaron Durbin
There are 2 methods currently available in coreboot to load ramstage from romstage: cbfs and vboot. The vboot path had to be explicitly enabled and code needed to be added to each chipset to support both. Additionally, many of the paths were duplicated between the two. An additional complication is the presence of having a relocatable ramstage which creates another path with duplication. To rectify this situation provide a common API through the use of a callback to load the ramstage. The rest of the existing logic to handle all the various cases is put in a common place. Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5087 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-11SMP: Add arch-agnostic boot_cpu()Kyösti Mälkki
We should not have x86 specific includes in lib/. Change-Id: I18fa9c8017d65c166ffd465038d71f35b30d6f3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5156 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-11Move hexdump32() to lib/hexdump.Kyösti Mälkki
Needs printk and is not a console core function. Change-Id: Id90a363eca133af4469663c1e8b504baa70471e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5155 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-09mtrr: only add prefetchable resources as WRCOMB for VGA devicesAaron Durbin
Be more conservative and only add VGA devices' prefetchable resources as write-combining in the address space. Previously all prefetchable memory was added as a write-combining memory type. Some hardware incorrectly advertises its BAR as prefetchable when it shouldn't be. A new memranges_add_resources_filter() function is added to provide additional filtering on device and resource. Change-Id: I3fc55b90d8c5b694c5aa9e2f34db1b4ef845ce10 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5169 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2014-02-06uart8250: Drop xmodem supportKyösti Mälkki
Unused and hard-coded to use uart8250 on IO. Change-Id: I3f84c50039a450a2ae97a5fd2af89992f8567e6c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5137 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-06ne2k: Move under drivers/netKyösti Mälkki
Change-Id: I978b6009c09c31be4429f57be40ef82f438f7574 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5135 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-06spkmodem: Move under drivers/pc80Kyösti Mälkki
Change-Id: I46eb17ab19cea8759b3e4822019285cbe907e83a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5134 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-06usbdebug: Move under drivers/usbKyösti Mälkki
Also relocate and split header files, there is some interest for EHCI debug support without PCI. Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06lib/memrange: Skip 0-sized resources.Vladimir Serbinenko
Change-Id: I44194153817b8e6b641e407fc4a9e0fd5bc3f318 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5152 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06memranges: add memranges_update_tag() functionalityAaron Durbin
The memranges_update_tag() function replaces all instances that are tagged with old_tag and update to new_tag. This can be helpful in the MTRR code by adjusting the address space if certain memory types cause the MTRR usage to become too large. Change-Id: Ie5c405204de2fdd9fd1dd5d6190b223925d6d318 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5150 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-05load_payload: Use 32-bit accesses to speed up decompression.Vladimir Serbinenko
Flash prefers 32-bit sequential access. On some platforms ROM is not cached due to i.a. MTRR shortage. Moreover ROM caching is not currently enabled by default. With this patch payload decompression is sped up by theoretical factor of 4. Test on X201, with caching disabled: Before: 90:load payload 4,470,841 (24,505) 99:selfboot jump 6,073,812 (1,602,971) After: 90:load payload 4,530,979 (17,728) 99:selfboot jump 5,103,408 (572,429) Change-Id: Id17e61316dbbf73f4a837bf173f88bf26c01c62b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5144 Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-01-30coreboot: config to cache ramstage outside CBMEMAaron Durbin
Haswell was the original chipset to store the cache in another area besides CBMEM. However, it was specific to the implementation. Instead, provide a generic way to obtain the location of the ramstage cache. This option is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM Kconfig option. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted with baytrail support. Also built for falco successfully. Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172602 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4876 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30cbmem: Export ACPI GNVS cbmem pointer in coreboot tableDuncan Laurie
This will make it possible for payloads to find the ACPI NVS region which is needed to get base addresses for devices that are in ACPI mode. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi with emmc in ACPI mode Change-Id: Ia67b66ee8bd45ab8270444bbb2802080d31d14eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5015 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-28rmodule: consolidate rmodule stage loadingAaron Durbin
There are 3 places rmodule stages are loaded in the existing code: cbfs and 2 in vboot_wrapper. Much of the code is the same except for a few different cbmem entry ids. Instead provide a common implementation in the rmodule library itself. A structure named rmod_stage_load is introduced to manage the inputs and outputs from the new API. BUG=chrome-os-partner:22866 BRANCH=None TEST=Built and booted successfully. Change-Id: I146055005557e04164e95de4aae8a2bde8713131 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174425 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4897 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-28cbmem: add reference code idsAaron Durbin
In order to identify the ram used in cbmem for reference code blobs add common ids to be consumed by downstream users. BUG=chrome-os-partner:22866 BRANCH=None TEST=Built and booted with ref code support. Noted reference code entries in cbmem. Change-Id: Iae3f0c2c1ffdb2eb0e82a52ee459d25db44c1904 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174424 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4896 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-27coreboot_table: don't add CMOS checksum twice.Vladimir Serbinenko
Checksum is already in cmos_layout.bin. No need to add it twice Change-Id: I6d12f35fd8ff12eee9a17365bbfab38845c09574 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4829 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-22CBMEM: Rename cbmem_reinit()Kyösti Mälkki
This function does not really initialize anything, but only checks for the TOC. Change-Id: I9d100d1823a0b630f5d1175e42a6a15f45266de4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4669 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-22CBMEM: Replace cbmem_initialize() with cbmem_recovery()Kyösti Mälkki
The replacement function confirms CBMEM TOC is wiped clean on power cycles and resets. It also introduces compatibility interface to ease up transition to DYNAMIC_CBMEM. Change-Id: Ic5445c5bff4aff22a43821f3064f2df458b9f250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4668 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-01-14lib: Add log2 ceiling functionAlexandru Gagniuc
Change-Id: Ifb41050e729a0ce314e4d4918e46f82bc7e16bed Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4684 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-14lib/hexdump: Take const void * and size_t as argumentsAlexandru Gagniuc
Representing a memory location as an unsigned long is specific to 32-bit architectures. It also doesn't make sense to represent a length assumed to be positive as a signed integer. With this change, it is no longer necessary to cast a pointer to unsigned long when passing it to hexdump. Change-Id: I641777d940ceac6f37c363051f1e9c1b3ec3ed95 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4575 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13lib: Make log2() available in romstage on ARM, not just x86Alexandru Gagniuc
On x86, log2() is defined as an inline function in arch/io.h. This is a remnant of ROMCC, and forced us to not include clog2.c in romstage. As a result, romstage on ARM has no log2(). Use the inline log2 only with ROMCC, but otherwise, use the one in clog2.c. Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4681 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-12lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_contentVladimir Serbinenko
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4659 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-01-06CBMEM: Fix allocation for static CBMEMKyösti Mälkki
CBMEM console buffer size is adjustable in menuconfig, but this would not correctly adjust the overall allocation made for CBMEM. HIGH_MEMORY_SIZE is aligned to 64kB and definitions are moved down in the header file as HIGH_MEMORY_SIZE is not used with DYNAMIC_CBMEM. Try to continue boot even if CBMEM cannot be created. This error would only occur during development of new ports anyways and more log output is better. Change-Id: I4ee2df601b12ab6532ffcae8897775ecaa2fc05f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4621 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-01-06CBMEM: Drop cbmem_base_check()Kyösti Mälkki
This function was for logging only, but we have both base and size already logged elsewhere. Change-Id: Ie6ac71fc859b8fd42fcf851c316a5f888f828dc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4620 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-06CBMEM ACPI: Move resume handlerKyösti Mälkki
Handler is ACPI/x86 specific so move details out of cbmem code. With static CBMEM initialisation, ramstage will need to test for S3 wakeup condition so publish also acpi_is_wakeup(). Change-Id: If591535448cdd24a54262b534c1a828fc13da759 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4619 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 02:38:40 +0000