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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Was accidentially removed in 6e50849
Change-Id: I090b6bc8863d17412cb1e23ac816c39f479290c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39937
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add missing port definition for the mSATA/WWAN mPCIe port,
set OC pin for internal ports to OC_SKIP, fix port
descrption for mPCIe/WLAN port, remove USB3 definition for
right type-A port as it is USB2 only.
Test: insert WiFi module into WWAN port, observe BT portion
detected and functional.
Change-Id: Ie39b99eeb0f605ff07d57c32189fb1f4183713e4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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_DCS, _DGS and _DSS are required by specification. However,
we never implemented them properly, and no OS driver com-
plained yet. So we stub them out and keep the traditional
behavior in case an OS driver checks for their existence.
The old implementations also only returned static values as
there never was any write to their GNVS variables. The TRAP()
that was called in one place is actually implemented by some
ThinkPad's SMI handler as docking event. However, as the call
precedes these SMI handlers in coreboot history, it's most
likely an accident.
Change-Id: Ib0b9fcdd58df254d3b2290900e3bc206a7abd92d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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The X210 EC reports battery values in broken mAh. These have to be
adjusted by 10000 * DGVO, as documented in
https://github.com/torvalds/linux/blob/master/drivers/acpi/battery.c.
Taken from https://github.com/harrykipper/coreboot, commits
2f68f138adb25605e5715896636cf33f6de5bd95
c1c72cc43708a6647f263a767c39cf3072908e20
Change-Id: Ie097272443b18b16c3937034f874d3b5a6bdd62a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39142
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Add USB ports for SD card reader, fingerprint reader,
and internal port.
- Enable PcieRpClkReqSupport on NVMe root port,
correct values for ClkReq/ClkSrc.
- Improve comment for M.2-2230 USB port (BT)
Parts derived from x210_test branch of HarryKipper's repo:
https://github.com/harrykipper/coreboot
Change-Id: Ib64629ada4726e5edc080608f71a51f56a9b747c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Derived from x210_test branch of HarryKipper's repo:
https://github.com/harrykipper/coreboot
Test: build/boot x210, test eDP, MiniDP, VGA outputs
Change-Id: Ie2b79b236a458ebd243c992d6e615e41930eeb50
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems,
based on a modern Kabylake CPU. It also ships with no firmware protection,
(IFD is fully unlocked, no protected regions are set, no Bootguard),
making it an ideal coreboot target. This port is based on the support for
the Skylake-based Purism Librem 13v3, with the following significant
changes:
* EC firmware is contained within the system SPI flash, and so a blob of
EC firmware must be injected to a defined location during image build.
* GPIO layout is different - this is currently just a raw import of the
GPIO configuration from the vendor firmware
* The system has two DIMMs, so an additional SPD address has been added
* The USB port layout is different
* The EC must be enabled at boot time through SuperIO-style logical device
configuration
* EC register layout is different, necessitating changes in the ACPI tables
* The HDA pins are different
* The genx_dec config is different
All hardware appears to work as expected, although the SD reader is
untested.
Signed-off-by: Matthew Garrett <mjg59@google.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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