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2018-05-09mb/a785e-i: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I15f160c1e30496461f7100e3bd3a2e2467c64c4a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08src/mainboard: Set ACPI OEM ID values to 6 characters longMartin Roth
Change OEM ID values to 6 characters to fix error compiling with IASL version 20180427. Also update table creator to 8 characters from 7. Change-Id: Id6c9a7b08dc4a9efeb69011393e29aa5a6bc54c4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-26mb/*/*/cmos.layout: Fix the values for the console levelArthur Heymans
Fix the values that were off by one. This was discovered when using postcar stage that prints with debuglevel BIOS_NEVER. Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-11AMD fam10: Link southbridge/amd/rs780/early_setup.cArthur Heymans
Removes rs780_before_pci_init() since it was a no-op anyway. Removes get_nb_rev() since this function is provided via a macro in the header. This Makes a lot of function non-static since the header has prototypes for these. Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-11-28AMD platforms: Fix ASL comment that implies "\_SB" is southbridgeMartin Roth
Change-Id: I6ee86396a1c5aaee248a275b42da801cedace586 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-31AMD boards: Fix function name (soft_reset) in messageJonathan Neuschäfer
Change-Id: Ia21a3e93712bd6b6780fe7308c6cf79c553f4e1b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-21superio/winbond/*: Unify w*_set_clksel_48()Keith Hui
This function is identical throughout all Winbond superios in the tree, so move it into superio/winbond/common/early_init.c, renamed from early_serial.c because it now does more than just early serial. Change all affected mainboards to use the unified function. Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-23AMD fam10 ACPI: Use common fixed sleepstates.aslKyösti Mälkki
SSFG was meant to be used as a mask to enable sleepstates _S1 thru _S4. However as a logical instead of bitwise 'and' operation was used, all the states were enabled if only one was marked available. Note that all boards incorrectly had SSFG == 0x0D that previously enabled ACPI S3 sleep state even when it was not available. Change-Id: Ia948becff079383cbf861468da9e8a3ebbf213cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-22AMD K8 fam10-15: Consolidate post_cache_as_ram callKyösti Mälkki
Change-Id: I5e7890aafbc8c80716ee49690e306482a482a863 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20573 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-07-06mainboard/[a-e]: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: Icca8bac5e67f83dfc5a8f5ef1cb87c6432e0a236 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-05src/amd: Add common definition of AMD ACPI MMIO addressTimothy Pearson
The bare ACPI MMIO address 0xFED80000 was used in multiple AMD mainboard files as well as the SB800 native code. Reduce duplication by using a centrally defined value for all AMD ACPI MMIO access. Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18032 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2016-12-26amd-based mainboards: Fix whitespace in _PTS commentsMarshall Dawson
Correct tabs that were intended as spaces. Change-Id: Idcf33d829f87a866b5ed880527102918d5b93842 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17905 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-12-06cpu/amd/mtrr.h: Drop excessive includesKyösti Mälkki
Change-Id: Id404bdab1f2361f1e7d20f7ee72111971863dddf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17736 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/x86/msr.h: Drop excessive includesKyösti Mälkki
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-10mainboard/advansus: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: Ib44bc66e02901dbde14361091a049f71c3ecb840 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16921 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-10-01mainboard/*/*/*/usb.asl: Use tabs for indentsElyes HAOUAS
Change-Id: Id46a0c4ca59dc7224c2eedd674ea3a5486509de1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16824 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-26mainboard/*/*/dsdt.asl: Use tabs for indentsElyes HAOUAS
Change-Id: Idef587d8261784e916e8d50f4336cbcfca39b9b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16730 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/a-trend - emulation: Add space around operatorsElyes HAOUAS
Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16616 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18AGESA vendorcode: Build a common amdlibKyösti Mälkki
Having CFLAGS with -Os disables -falign-function, for unlucky builds this may delay entry to ramstage by 600ms. Build the low-level IO functions aligned with -O2 instead. Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14414 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-09ASL: Fix HPBA shadowing.Vladimir Serbinenko
Store (HPBA, HPBA) had no effect. Rename one of HPBA to avoid shadowing. Change-Id: I54bfa7bcb3e05c28fe8a257825af56527dbf663e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13622 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-10ACPI: Work around IASL warning reading/writing same registerMartin Roth
The newer versions of IASL are unhappy when an operator has the same object as both source and destination. The warning can be completely disabled with a command line argument, but in general, I'd really rather not just disable warnings. The bits in this register are write 1 to clear, so reading and writing the same register is what we want to do. Instead, store it in a temporary register then write it in a second operation. Fixes warning: dsdt.aml 1396: Store(PWST, PWST) Warning 3023 - ^ Duplicate value in list (Source is the same as Target) Change-Id: I52d73d4431db237be83016d67cd397f31b53d9c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10ACPI: Fix IASL Warning about unused method for _OSI checkMartin Roth
According to the ACPI Spec for CondRefOf, the result argument is optional. In all of these locations, it was getting set but not used, creating a warning in new versions of IASL. Since it's an optional argument, just remove it. dsdt.aml 22: if(CondRefOf(\_OSI,Local1)) Warning 3144 - ^ Method Local is set but never used (Local1) Change-Id: I07f49ac5a3708838d1c4a7216dfb11acc415c881 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gartTimothy Pearson
Change-Id: Ia24102e164eb5753ade3f9b5ab21eba2fa60836b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12046 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequenceTimothy Pearson
This fixes Family 15h multiple package support; the previous code hung in CAR setup and romstage when more than one CPU package was installed for a variety of loosely related reasons. TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors and several different RDIMM configurations. Change-Id: I171197c90f72d3496a385465937b7666cbf7e308 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12020 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-05mainboard: Remove last_boot NVRAM optionTimothy Pearson
The last_boot NVRAM option was deprecated and removed in commit 3bfd7cc6. Remove the last_boot option from all affected mainboards to eliminate user confusion. Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12316 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
TEST: Booted ASUS KGPE-D16 with single Opteron 6380 * Unbuffered DDR3 DIMMs tested and working * Suspend to RAM (S3) tested and working Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02cpu/amd: Move model_10xxx to family_10h-family_15hTimothy Pearson
Change-Id: I34501d3fc68b71db7781dad11d5b883868932a60 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11965 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-29mainboard: Convert #ifdef to IS_ENABLED in get_bus_conf.cTimothy Pearson
Change-Id: I254e9e9e65519edcf4d3f1ecc385af16d18c2367 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12208 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-24amd/acpi: Clean up SMBus references.Tobias Diedrich
Replace the AMD SMBus section with the equivalent SB800 smbus.asl include or remove already commented-out sections. Verified by running the cpp preprocessor over the DSDTs and diffing the results against this patch. The only change is in src/mainboard/siemens/sitemp_g1p1/dsdt.asl, where someone added RADD and SADD to the OpRegion, but those are unused, so removing them is fine. Change-Id: I074c8a1ed1c9a944d4988752bd0fc42c199c766c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10618 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
While the romstage code flow is not consistent across all mainboards/chipsets there is only one way of running ramstage from romstage -- run_ramstage(). Move the timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. TS_END_ROMSTAGE still present in timestamp table. Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11700 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-23AMD Kconfig: Remove QRANK_DIMM_SUPPORT from unsupported platformsMartin Roth
The AMD K8 northbridge uses the Kconfig symbol QRANK_DIMM_SUPPORT, but the symbol was used on a number of Family 10 boards as well. AMD Family 10 doesn't use this Kconfig symbol for anything. I verified that the symbol wasn't used actually getting used in any of these platforms. Fixes Kconfig warnings for these 19 mainboards: warning: (BOARD_SPECIFIC_OPTIONS...) selects QRANK_DIMM_SUPPORT which has unmet direct dependencies (NORTHBRIDGE_AMD_AMDK8) Change-Id: I454992a4975566fd6439a21f5a800d0cfa1b4d3b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11300 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-06-05AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0Kyösti Mälkki
If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus is the first to scan and it will be assigned with bus number 0. If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range of bus numbers instead of assigning consecutive numbers across all the links. All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge. Follow-up can easily drop this if we find this is dictated by architecture. Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8366 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-28Kconfig whitespace fixesMartin Roth
trivial whitespace fixes. Mostly changing leading spaces to tabs. Change-Id: I0bdfe2059b90725e64adfc0bdde785b4e406969d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18kconfig: automatically include mainboardsStefan Reinauer
This change switches all mainboard vendors and mainboards to be autoincluded by Kconfig, rather than having to be mentioned explicitly. This means, vendor and mainboard directories are becoming more "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree mainboards / components to be built with a given coreboot version (given that the API did not change) Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a Reviewed-on: http://review.coreboot.org/9295 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-01mainboards/amdfam10: Copy DIMM information to cbmem after romstageTimothy Pearson
src/northbridge/amd/amdfam10: Add amdmct_cbmem_store_info() function. Change-Id: I07376e276e3e9e3247d2576a09e58780d32a3a76 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9138 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-03-21mainboards/amd/fam10: Add romstage timestampsTimothy Pearson
Example output: 1:start of rom stage 542 2:before ram initialization 193,989 (193,447) 3:after ram initialization 3,319,114 (3,125,124) 4:end of romstage 3,320,004 (889) Change-Id: Idcde7dc4c7a1d6c3118c82b67e8c2fcd4a07553b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8776 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-19cpu/amd/model_10xxx: Add support for early cbmemTimothy Pearson
mainboards/amd/fam10: Initialize cbmem area after raminit When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE When GFXUMA is disabled, CBMEM is placed at TOM This matches the behaviour present before conversion to early CBMEM. The CBMEM location code implicitly assumes TOM does not change between romstage and ramstage. TOM is set by romstage raminit, and is never changed by romstage or ramstage afterward. As the CBMEM location is positioned at a specific offset from TOM that is known to both romstage and ramstage early CBMEM is safe on Fam10h systems. TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp tables from romstage and cbmem log tables from ramstage. Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8489 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-03-09AMD fam10: Always have AMDMCTKyösti Mälkki
Also drop some more #if UNUSED_CODE. Change-Id: I1bbe96a65c9240636ff7cfaf70c2ecbfb3aee715 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8551 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-16mainboard/cmos: Kill off unused boot_* parametersTimothy Pearson
Change-Id: I19d6b56e3ac5e6e7946648b97c86a223b748e3bd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8460 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/cmos: Move ECC variables out of fallback mechanism byteTimothy Pearson
Change-Id: Icebc12d8f83494150a7bdd3adcc168d7b48b2e68 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8458 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/cmos: Delete obsolete commented parametersTimothy Pearson
Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8459 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-02-14AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configurationKyösti Mälkki
A set of pins can be configured for GPIO or (parallel) PCI bridge use. When requested configuration is 0:14.4 enabled, register programming must be done before attempting to enumerate devices behind the bridge. When requested configuration is 0:14.4 disabled, we must not even temporarily enable pins for PCI use to avoid spurious GPIO state changes. As our PCI subsystem currently does not configure visible PCI bridges that are marked disabled, we cannot mark 0:14.4 disabled just yet but need to handle pcengines/apu1 as a special case. Drop related dead code. Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8329 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-03amd/model_10xxx: Drop AMD_UCODE_PATCH_FILE selectionKyösti Mälkki
Include microcode updates in CBFS for every CPU revision the platform can support, as changing to different CPU revision should not require a coreboot rebuild. This increases CBFS usage from 2 kB to 14 kB. Change-Id: I6bf90221a688f1a54e49641ce3ba378c5bf659f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4521 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
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