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2009-06-30This patch unifies the use of config options in v2 to all start with CONFIG_Stefan Reinauer
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-19Undo my ugly commit that added uses clauses in lots of places instead of one.Myles Watson
Fix configuration of all boards. (Abuild tested) Hopefully fix compilation of PPC boards (they've never compiled for me.) Apologize profusely. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-17Fix configuration of boards that didn't have uses CONFIG_USE_INIT. Trivial.Myles Watson
Abuild tested with -C. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06When I started refactoring mainboard Config.lb, I added two differentCarl-Daniel Hailfinger
files for targets without failover: src/config/nofailovercalculation.lb (64 kB XIP) src/config/nofailovercalculation128.lb (128 kB XIP) Targets with other XIP sizes were ignored. This patch moves XIP size back into mainboard code. Benefits from this patch: - src/config/nofailovercalculation128.lb is no longer needed - Targets with XIP sizes besides 64k and 128k benefit from refactoring - Conceptually, this makes the include files pure calculation files without settings. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21Thanks to Myles' patch adding support for include statements,Carl-Daniel Hailfinger
refactoring Config.lb became possible. Factor out ROM size calculation from Config.lb. This patch converts 87 boards (with and without USE_FAILOVER_IMAGE), but it has to work around a parser bug. 89 files changed, 209 insertions(+), 2415 deletions(-) A total of 2206 removed lines. Abuild works for all changed boards on khepri. Myles writes: I've tested serengeti for the failover portion and s2892 for the nofailover portion. ldoptions are exactly the same and they both boot the same. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14v2/src romfs->cbfs renamePeter Stuge
This also has the config tool changes in v2/util. Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31Add the CONFIG_ROMS config variable. Ronald G. Minnich
Tested under abuild, causes no trouble. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-18Carl-Daniel's part:Carl-Daniel Hailfinger
This patch converts mainboard_$VENDOR_$BOARD_ops to mainboard_ops and mainboard_$VENDOR_$BOARD_config to mainboard_config. Ron's part: The config change that makes the naming change not break every build. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-04This changes the python generated makefilesCarl-Daniel Hailfinger
targets/*/*/Makefile targets/*/*/normal/Makefile targets/*/*/fallback/Makefile to use a common copy of romcc, and to leave this compiler untouched by 'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ . 'make clean' in targets/*/*/ will clean romcc. Thanks to Mats for the initial idea and implementation of a tool to do this. This patch has almost the same behaviour as the original tool without having to run the tool each time. Tested for abuild-friendliness. The patch saves ~10-12 seconds for every target using romcc. For a full abuild run, this is ~20% time saved. For the first 38 abuild targets, total build time is down to 13m24s instead of 16m22s on my machine. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29Now coreboot performs IRQ routing for some boards.Nikolay Petukhov
You can see this by executing commands like this: grep -r pci_assign_irqs coreboot/src/* This basically AMD/LX based boards: pcengines/alix1c, digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800. Also for AMD/GX1 based boards need a patch [http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch] for the right IRQ setup. AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320, bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p. I have two ideas. 1. Delete duplicate code from AMD/LX based boards. 2. Add IRQ routing for AMD/GX1 boards in coreboot. The pirq.patch for IRQ routing logically consist from of two parts: First part of pirq.patch independent from type chipsets and assign IRQ for ever PCI device. It part based on AMD/LX write_pirq_routing_table() function. Second part of pirq.patch depends of type chipset and set PIRQx lines in interrupt router. This part supports only CS5530/5536 interrupt routers. IRQ routing functionality is included through PIRQ_ROUTE in Config.lb. Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on TeleVideo TC7020, see http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Rename almost all occurences of LinuxBIOS to coreboot. Stefan Reinauer
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
code is changed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13Add support for the Advantech PCM-5820.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-01drop unsupported unfinished mainboard Advantech SOM GX DB533-CRichard Smith
Signed-off-by: Richard Smith <smithbone@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-27Fix the CHIP_NAME() entries of all mainboards to have the same formatUwe Hermann
and (hopefully) the correct canonical name of the vendor and board. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24Change all occurences of NSC to nsc in the code. The next commitUwe Hermann
will then rename the src/superio/NSC directory to src/superio/nsc. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-01- Adds support for the Advantech eval board. Configuration was producedRichard Smith
on a SOM-DB2301 baseboard with a SOM-2354 cpu module. - Also does a slight tweak to the ram test code to make it more obvious when it fails. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1