| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-05-05 | AGESA: Implement EmptyHeap() | Kyösti Mälkki |
| 2014-05-05 | AGESA fam12: Add GetHeapBase() | Kyösti Mälkki |
| 2014-01-15 | Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR | Kyösti Mälkki |
| 2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
| 2013-01-16 | Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITS | Martin Roth |
| 2013-01-11 | AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITS | Zheng Bao |
| 2012-07-25 | AMD Family15tn: Set the mask of MTRR to 0000FFFXX0000800 | zbao |
| 2011-11-01 | remove trailing whitespace | Stefan Reinauer |
| 2011-06-28 | Add the AMD Torpedo mainboard | efdesign98 |
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index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |