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2010-03-22printk_foo -> printk(BIOS_FOO, ...)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18Remove remaining uses ofPatrick Georgi
HAVE_FAILOVER_BOOT HAVE_FALLBACK_BOOT USE_FAILOVER_IMAGE USE_FALLBACK_IMAGE Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18Rework boolean expression (DeMorgan and all) forPatrick Georgi
better readability. Also remove failover.c files in mainboards, as they're not used anymore (and useless, too) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18Remove fallback/normal handling in mainboards'Patrick Georgi
romstage.c like r5255 did for failover/fallback/normal mainboards. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17Remove failover/fallback/normal handling in mainboards'Patrick Georgi
romstage.c. That's newconfig stuff. 1. In failover_process(), I removed the fallback/normal selection logic and kept the remaining hardware init in. The if-clauses' conditions are reverted to match. Remove #if failover||fallback guard. 2. Change cache_as_ram_main() to first call failover_process, then real_main unconditionally. 3. Move failover_process's code to the beginning of real_main, remove failover_process and its call in cache_as_ram_main. 4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same arguments, so no problem with that) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17trivial warning fixes, mostly for ACPI codeStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16Add entries of RS780, SB700, Mahogany, Mahogany_fam10 into theZheng Bao
Makefile and Kconfig. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16The code can run on the Mahogany board, which is one of sample boardsZheng Bao
made by AMD. Its major features are: CPU: * AMD AM2+ * AMD Athlon 64 x2 * AMD Athlon 64 FX * AMD Athlon 64 * AMD Sempron CPUs System Chipset: * RS780E * SB700 On Board Chipset: * BIOS - SPI * Azalia CODEC - Realtek ALC888 * LPC SuperIO - ITE8718F(GX). * LAN - REALTEK 8111C * TPM - SLB9635TT1.2 Main Memory: * DDR II * 4 (Max 4GB) Expansion Slots: * PCI Express X16 slot*2 (PCI-E X8 Bus) * PCI Express X4 Slot*1 Intersil PWM: * Controller - Intersil 6323 Note: 1. The only difference to mahogany is the CPU is changed to K8 family 10. 2. The main structure of the code is based on serengeti_cheetah_fam10. I am a rookie to fam10. I am still confused about CONFIG_HT_CHAIN_UNITID_BASE and CONFIG_HT_CHAIN_END_UNITID_BASE. I set them as the way dbm690t does. And I have to modify the some fam10 code (see the patch ht_chain_unitid_base.patch). I dont know how to solve this. Please help. Updated findings: In h3finit.c, the code goes the AMD_CB_ManualBUIDSwapList(). The swaplist is {0x00, 0x00, 0xFF, 0x00, 0xFF}. I am trying to find the meaning of the list. The amdht wrapper needs to modify definitely. 3. With fam10 processor, the HT link can work in HT3. 4. The ACPI _PSS table is set staticly. The auto configuaration process doesnt seem to work correctly. 5. Currently the fam10 code in coreboot doesn't support DDR3. If you happen to get a board with DDR3 and you don't have the patience to wait, please find another board with DDR2. 6. It will take "Uncompressing image to RAM" about 1 minute. I know it is a issue for a long time. I disable the compressing currently. When the problem is fixed, we can re-enable it. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-161. Features of mahogany.Zheng Bao
The code can run on the Mahogany board, which is one of sample boards made by AMD. Its major features are: CPU (only K8 system): * AMD AM2+ * AMD Athlon 64 x2 * AMD Athlon 64 FX * AMD Athlon 64 * AMD Sempron CPUs System Chipset: * RS780E * SB700 On Board Chipset: * BIOS - SPI * Azalia CODEC - Realtek ALC888 * LPC SuperIO - ITE8718F(GX). * LAN - REALTEK 8111C * TPM - SLB9635TT1.2 Main Memory: * DDR II * 4 (Max 4GB) Expansion Slots: * PCI Express X16 slot*2 (PCI-E X8 Bus) * PCI Express X4 Slot*1 Intersil PWM: * Controller - Intersil 6323 2. The ACPI feature is already added. I suggest that firstly we can test the board without the ACPI by setting the HAVE_ACPI_TABLE as 0. With Rev F processor, the HT link can only work in HT1, whose max frequency is 1GHz. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-11Replace clear_memory with memset.Myles Watson
Replace set_init_ram_access with the call to set_var_mtrr. Remove unused #include statments. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-05This patch is from 2009-10-20Uwe Hermann
Convert all DEBUG_SMBUS, DEBUG_SMI, and DEBUG_RAM_SETUP custom and local #defines into globally configurable kconfig options (and Options.lb options for as long as newconfig still exists) which can be enabled by the user in the "Debugging" menu. The respective menu items only appear if a board is selected where the chipset code actually provides such additional DEBUG output. All three variables default to 0 / off for now. Also, drop a small chunk of dead/useless code in the src/northbridge/via/cn700/raminit.c file, which would otherwise break compilation. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Reworked to still apply to trunk, added X86EMU_DEBUG (and make the x86emu/yabel code only work printf instead of a redefined version of printk and Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-01Drop unused doit.sh files (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-01- Add rules that build either 4 or 5 ssdts (only those variants exist in the ↵Patrick Georgi
board now) - Change ACPI_SSDTX_NUM to either 4 or 5 for boards that have ssdtX.asl files, according to the number of ssdtX.asl there. - Remove custom ssdt rules Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-28disable AP_CODE_IN_CAR. The K8 code has an alternate code path to do the job,Stefan Reinauer
and it's not working anyways. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-28- Add config flag for boards that have their own fadt.cPatrick Georgi
This should eventually go, as fadt seems to be better put into the southbridge - Add config flag for boards that have get_bus_conf.c Might be cleaned out as well, no idea - Use flags where appropriate. - Move the following rules to src/arch/i386/Makefile.inc: - fadt.o - dsdt.o - acpi_tables.o - get_bus_conf.o - Rename objs_dsl_template in toplevel Makefile to the more appropriate objs_asl_template - Remove all Makefiles that are empty now, which includes src/mainboard/Makefile.k8_CAR.inc and src/mainboard/Makefile.k8_ck804.inc and the include statements that used these files. - Add workaround to intel/xe7501devkit: It uses ACPI in an unusual way: It adds a MADT, but no DSDT. As this is highly unusual, I didn't want to add explicit support for that scenario (and encourage such uses that way), and added a dummy dsdt.asl instead. It will be linked to dsdt.o, but not linked into the final binary. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-27- make HAVE_HARD_RESET match what newconfig didPatrick Georgi
- introduce BOARD_HAS_HARD_RESET and use it if a board provides hard_reset in $(MAINBOARDDIR)/reset.c, instead of some chipset component - move a couple of rules out of the mainboards' Makefiles into src/arch/i386/Makefile.inc: initobj-y += crt0.o obj-y += mainboard.o obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o obj-$(CONFIG_BOARD_HAS_HARD_RESET) += reset.o - remove Makefile.incs that are empty (or comment-only) after these changes, incl. Makefile.romccboard.inc (and references to it) - Make include not fail if Makefile.inc doesn't exist. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-25Move the ldscripts logic to src/arch/i386/Makefile.incPatrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-25Unify crt0s setup to src/arch/i386/Makefile.inc. This variablePatrick Georgi
is not something users have to concern themselves with anymore. Also fixes some wrong romstrap configs for boards, fixing a couple of them. Also add "make printcrt0s" target for debugging crt0s when updating modified checkouts. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-23Only handle code as "driver" that actually uses our driverPatrick Georgi
infrastructure (special linking, data structures, etc) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22fix builds...Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-15Various license header consistency fixes (trivial).Uwe Hermann
- Consistently use the same wording and formatting for all license headers. - Remove useless whitespace, add missing whitespace, fix indentation. - Add missing "This file is part of the coreboot project." where needed. - Change "(C) Copyright John Doe" to "Copyright (C) John Doe" for consistency. - Add some missing "(C)" strings and copyright years where needed. - Move random comments and file descriptions out of the license header. - Drop incorrect file descriptions completely (e.g. lpc47m10x/Makefile.inc). There should be no changes in _content_ of the license headers, if you spot such changes that's a bug, please report! Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-09Actually set HAVE_OPTION_TABLES for the boards that need it.Patrick Georgi
(See last commit) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-09Move all the copies of the romstage.inc rule toPatrick Georgi
src/arch/i386/Makefile.inc For that to work, I had to: - Add a CONFIG_ROMCC variable - Set that variable on all ROMCC boards - conditionally choose romcc or gcc rule based on that variable - remove those two rules from all the boards' Makefiles - switch a couple of boards to HAVE_OPTION_TABLE, as they actually have. Also remove the duplication of rules with the sole difference of if they depend on option_table.h or not. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-09Port of CS5536 early UART setup from v3.Edwin Beasant
Permit early setup of COM2 Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-08Clean up ACPI:Patrick Georgi
- unify all iasl related rules into the toplevel Makefile - build a filesystem standard for ACPI files and use it - pass ACPI sources through cpp, so constants can be shared between C and ACPI more easily - use cpp's #include instead of ACPI's Include() so cpp gets the whole picture Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-08straighten naming scheme for application processor rom stage files.Stefan Reinauer
Apparently they are not used. If you have any of the boards touched in this commit, please test and report (so we can figure out what to do with the ap_romstage.c files in general) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-08janitor task: unify and cleanup naming.Stefan Reinauer
cache_as_ram_auto.c and auto.c are both called "romstage.c" now. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07fix further build.h dependencies that were undetected before we enabled it on Stefan Reinauer
our parallel build server ;-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07newconfig is no more.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-04Move CAR settings for all GX1, GX2, LX and Intel Slot2 boards to the CPU.Stefan Reinauer
This automatically adds the settings for those boards that didn't have settings at all yet. Also, small fixup to compareboard. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> --> Please help porting all boards from newconfig to Kconfig <-- This is a lot of janitor work and we can use your helping hands. The sooner we can get rid of Kbuild, the better. The KBuild report on the mailing list shows the config differences between newconfig and Kconfig. In theory, all Kconfig configs should be equal to their newconfig pendant. In practice it's better to come close but stay clean. --> Please help porting all boards from newconfig to Kconfig <-- git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-30* fix crt0s/ldscripts paths to fix out of tree build.Stefan Reinauer
* fix iasl output directory for i945 boards (patch for moving it to the mainboard directory will follow) * coreboot_table.c: lb_mainboard can be static * coreboot_table.c: dump memory table in debug and spew mode * fix a warning in bootblock.c * don't include arch/i386/init in arch/i386/Makefile.inc * announce generation of crt0_includes.h * allow overriding $(obj) * drop unused src_types from Makefile * correctly use hostname -s instead of hostname for COMPILE_HOST Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-26- Clean up and comment writing of MSRs for cache control (Backport from v3)Edwin Beasant
- Invalidate Cache Tags (by means of in-place rewrite of cache data) which allows CAR data to be flushed to RAM - Re-enable cache after flush of CAR to RAM Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-25Fix ACPI build on a couple of boards (now that it's active)Patrick Georgi
Fix timer handling on amd/sc520 systems Match UDELAY_* configuration of newconfig in Kconfig Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-25More Kconfig changes to improve match with newconfig:Patrick Georgi
DIMM_SUPPORT APIC_ID_OFFSET ACPI_SSDTX_NUM IRQ_SLOT_COUNT MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID (except msi/ms9185) MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID MEM_TRAIN_SEQ HAVE_ACPI_RESUME Also remove MMX (kconfig specific) and HAVE_MOVNTI and IOAPIC (which we deliberately differ in kconfig) from compareboard report. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-25Align several kconfig options to match newconfig:Patrick Georgi
HT_CHAIN_UNITID_BASE HT_CHAIN_END_UNITID_BASE SB_HT_CHAIN_ON_BUS0 SB_HT_CHAIN_UNITID_OFFSET_ONLY MAX_CPUS MAX_PHYSICAL_CPUS ROM_SIZE TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 Also hook up asus/p2b-ds Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-18Move all IOAPIC selection to southbridges, and remove themPatrick Georgi
from mainboards. Some adaptations were necessary after the IOAPIC cleanup, so this should fix the build. Fix intel/d945gclf build, which was missing some ACPI component. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16coreboot used to have two different "APIs" for memory accesses:Stefan Reinauer
read32(unsigned long addr) vs readl(void *addr) and write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr) read32 was only available in __PRE_RAM__ stage, while readl was used in stage2. Some unclean implementations then made readl available to __PRE_RAM__ too which results in really messy includes and code. This patch fixes all code to use the read32/write32 variant, so that we can remove readl/writel in another patch. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-05* Explicitly add __PRE_RAM__ where it should be added.Stefan Reinauer
* Don't implicitly add __PRE_RAM__ in romcc. Fixes intel/xe7501devkit Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-31romcc:Patrick Georgi
- Set __PRE_RAM__ define per default - Properly handle ignored (#ifdef'd out) #include lines amd/serengeti_cheetah_fam10: - write ACPI files to $(obj) instead of the top dir (alias $(CURDIR)) tinybootblock: - provide a way to define code that should be added to the bootblock, to map the entire ROM for use by CBFS amd/model_fxx, amd/model_10xxx: - add CONFIG_SSE walkcbfs.S: - eliminate the use of two registers, to make space for romcc to wiggle amd/serengeti_cheetah_fam10: - use the enable_rom framework. not entirely functional yet Boot-tested on emulation/qemu-x86 Build-tested on amd/serengeti_cheetah_fam10 amd/serengeti_cheetah_fam10 fails in amdht/ somewhere, but builds Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-18Clean up amd/dbm690t and kontron/986lcd-m some more (notPatrick Georgi
fully). Also fix the kconfig build for HAVE_ACPI_RESUME. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-27Eliminate special case id.inc/id.lds in favor of a configuration variable ↵Patrick Georgi
ID_SECTION_OFFSET which is normally set to 0x10 (the current default) and set to 0x80 (the current alternative) where necessary (if romstraps get in the way). For Kconfig, the special case is set per southbridge (as these define the necessity for this workaround), for newconfig it's added to each single board. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-27Make newconfig and kconfig agree on MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_IDPatrick Georgi
Usually, this means adding values to Kconfig, but in a few cases, adding values to newconfig, too (which doesn't hurt). Also really hook up tyan/s2850 and tyan/s2875 to kconfig, and have them still build. Trivial and stupid kconfig changes, just lots of them. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06Remove drivers/pci/onboard. The only purpose was for option ROMs, which areMyles Watson
now handled more generically using CBFS. Simplify the option ROM code in device/pci_rom.c, since there are only two ways to get a ROM address now (CBFS and the device) and add an exception for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06Remove some white space and comment differences from devicetree.cb and Config.lbMyles Watson
files. These boards have non-trivial differences: gigabyte/m57sli kontron/986lcd-m dell/s1850 via/epia-m700 Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.Uwe Hermann
Since we have CBFS setting rom_address in board files is no longer necessary. Also, drop vga_rom_address from RS690 completely, it was never used in the code. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06Split the two usages of __ROMCC__:Myles Watson
__ROMCC__ now means "Don't use prototypes, since romcc doesn't support them." __PRE_RAM__ means "Use simpler versions of functions, and no device tree." There are probably some places where both are tested, but only one is needed. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26Define some variables that were not defined. There are a couple left.Myles Watson
Do kbuildall then grep not.defined kbuildall.results/* The interesting ones were GENERATE_* I had to put them in twice to make it work correctly: once outside the menu setting the defaults, and once inside the menu. Now they show up when they should, and are always defined Define HAVE_INIT_TIMER to only exclude the three boards that define it to be 0 in newconfig. Define MEM_TRAIN_SEQ to be an integer and set it correctly. Remove CAR_FAM10 and just depend on NORTHBRIDGE_AMD_AMDFAM10 MOVNTI is a performance enhancement, and should default to 0 so it doesn't break boards that forget to define it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24Major cleanups of the hard_reset() code and config in coreboot.- supermicro/x6dhe_g/auto.c
- Drop unused "#object reset.o" entries. - Use CONFIG_HAVE_HARD_RESET for all "object reset.o" entries. - Drop dead/commented code, i.e. useless hard_reset() from: - supermicro/x6dhe_g/auto.c - supermicro/x6dhe_g2/auto.c - supermicro/x6dhe_g2/auto.updated.c - supermicro/x6dhr_ig/auto.c - supermicro/x6dhr_ig2/auto.c - digitallogic/msm586seg/auto.c - dell/s1850/auto.c - Add "obj-$(CONFIG_HAVE_HARD_RESET) += reset.o" to kconfig files of boards that actually have a reset.c file. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24move all register fram definitions to arch/register.hStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-23Drop dead K8_SCAN_PCI_BUS code. It's a bad idea to scan the PCI busses beforeMyles Watson
RAM is initialized, and no one does it. Trivial. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 05:34:54 +0000