| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-11-12 | sb/intel/i82801gx: Add common LPC decode code | Arthur Heymans |
| 2019-06-06 | sb/intel/i82801gx: Detect if the southbridge supports AHCI | Arthur Heymans |
| 2019-06-05 | mb/*/devicetree.cb: Remove unavailable PCIe ports | Arthur Heymans |
| 2019-01-24 | src/mb/asrock/../g41m-s3: Remove spurious devices | Angel Pons |
| 2018-11-12 | mb/*/*: Harmonise FD and devicetree on boards featuring ICH7 | Arthur Heymans |
| 2018-10-18 | src/mainboard: Remove unneeded whitespace | Elyes HAOUAS |
| 2018-09-28 | src/mb/asrock/g41c-gs: Add variant g41m-s3 | Angel Pons |
| 2018-09-25 | mb/asrock/g41m_vs3_r2: Add mainboard | Arthur Heymans |
| 2018-09-18 | mb/asrock/g41c-gs: Link separate gpio.c files | Arthur Heymans |
| 2018-09-15 | mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree | Arthur Heymans |
| 2018-07-22 | mb/asrock/g41c-gs: Add g41m-gs variant | Arthur Heymans |
| 2018-07-22 | mb/asrock/g41c-gs: Add the revision 1 variant | Arthur Heymans |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |