coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-11-18	sb/intel/bd82x6x: Make the pch_enable_lpc hook optional	Arthur Heymans
2019-11-18	nb/intel/sandybridge: Make the mainboard_rcba_config hook optional	Arthur Heymans
2019-11-18	nb/intel/sandybridge: Make the mainboard_early_init hook optional	Arthur Heymans
2019-11-15	nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK	Arthur Heymans
2019-11-15	nb/intel/x4x: Move boilerplate romstage to a common location	Arthur Heymans
2019-11-14	mb//(ich7/x4x): Use common early southbridge init	Arthur Heymans
2019-11-12	sb/intel/i82801gx: Add common LPC decode code	Arthur Heymans
2019-11-11	mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'	Elyes HAOUAS
2019-11-04	mb/asrock/h110m/devicetree: fix VR config info	Maxim Polyakov
2019-11-04	mb/asrock/h110m: use SSDT generator for SuperIO	Maxim Polyakov
2019-11-04	sb/intel/lynxpoint: Use sb/intel/common/platform.asl	Arthur Heymans
2019-11-04	mb//{i82801gx}: Use sb/intel/common/acpi/platform.asl	Arthur Heymans
2019-11-04	mb//{bd82x6x/ibexpreak}: Use sb/intel/common/acpi/platform.asl	Arthur Heymans
2019-11-03	mb/intel/{i82801gx,x4x}: Don't select ASPM options	Arthur Heymans
2019-11-01	soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi	Subrata Banik
2019-10-31	mb/asrock/h110m: configure SuperIO Deep Sleep	Maxim Polyakov
2019-10-27	src/mainboard: change "unsigned" to "unsigned int"	Martin Roth
2019-10-16	sb/intel/bd82x6x/lpc: Set up default LPC decode ranges	Arthur Heymans
2019-10-11	sb/intel/i82801gx: Move CIR init to a common place	Arthur Heymans
2019-10-02	soc/intel/skylake: devicetree: introduce PchHdaVcType fsp parameter	Michael Niewöhner
2019-09-14	mb/asrock/h110m: configure SuperIO global registers	Maxim Polyakov
2019-09-14	mb/asrock/h110m: configure GPIOs in SuperIO chip	Maxim Polyakov
2019-09-14	mb/asrock/h110m: enable ACPI LDN in SuperIO	Maxim Polyakov
2019-09-14	mb/asrock/h110m: set I/O Range for SuperIO HWM	Maxim Polyakov
2019-09-09	mb/asrock/h110m: add missing pci devices to tree	Maxim Polyakov
2019-09-09	mb/asrock/h110m: disable unused sata ports	Maxim Polyakov
2019-09-09	mb/asrock/h110m: disable unused serial buses	Maxim Polyakov
2019-09-09	mb/asrock/h110m: remove unsed i2c_voltage settings	Maxim Polyakov
2019-09-09	mb/asrock/h110m: use VR_CFG_AMP() macro to set PSI threshold	Maxim Polyakov
2019-09-09	mb/asrock/h110m: fix VR domains configuration	Maxim Polyakov
2019-09-01	mb/asrock/h110m: rewrite gpio config using macros	Maxim Polyakov
2019-08-26	soc/intel: Use common romstage code	Kyösti Mälkki
2019-08-20	mb/{asrock,intel,purism}: Copy channel arrays separately	Jacob Garber
2019-08-18	cpu/intel: Enter romstage without BIST	Kyösti Mälkki
2019-07-19	sb/intel/{bd82x6x\|ibexpeak}: Drop p_cnt_throttling_supported	Patrick Rudolph
2019-07-13	intel/haswell: Replace monotonic timer	Kyösti Mälkki
2019-06-27	mb/asrock/h110m: set serirq_mode to continuous mode	Maxim Polyakov
2019-06-21	mb/asrock/h110m: Correct Kconfig symbol selection	Angel Pons
2019-06-21	soc/intel/skylake: Clean up Kconfig	Arthur Heymans
2019-06-06	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans
2019-06-05	mb/*/devicetree.cb: Remove unavailable PCIe ports	Arthur Heymans
2019-05-20	sb/amd/cimx/sb800: Get rid of power button device in coreboot	Paul Menzel
2019-05-12	mb/asrock/h81m-hds: Drop now obsolete libgfxinit override	Nico Huber
2019-05-12	nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGE	Nico Huber
2019-04-23	sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock	Arthur Heymans
2019-04-23	nb/intel/sandybridge: Drop pch.h from sandybridge.h	Patrick Rudolph
2019-04-19	src/mb/Kconfig: Fix PCI subsystem IDs	Elyes HAOUAS
2019-04-13	sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB	Patrick Rudolph
2019-04-11	mb/asrock/h110m: Add virtual LDN for SuperIO to DT	Maxim Polyakov
2019-04-06	mb/asrock/h110m: Add PEG Gen3 support	Maxim Polyakov