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2014-01-29AGESA boards: Clean up definition of BIOS_SIZE in platform_cfgEdward O'Callaghan
Clean up vendor code from hard coded #define if-def chain with a pre-processor shift and subtract. Change-Id: Ibce34ab576d7db8586a6ec8f9b2460268e0e1878 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/4811 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-24asrock/e350m1/board_info.txt: Specify ROM socket and Flashrom support.Vladimir Serbinenko
Based on info by Kevin O'Connor. Change-Id: I21d447fec976e0ee967ba64b0f506c97c22917a3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4765 Tested-by: build bot (Jenkins) Reviewed-by: Kevin O'Connor <kevin@koconnor.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-22board_info.txt: Classify almost all remaining boards.Vladimir Serbinenko
Based on info from commit messages (most devel/eval boards are mentioned as such in commit message) and information from vendor sites (mostly based on form factor). Classification for siemens/sitemp_g1p1 is based on info by Nico Huber. For Google boards based on info from ML posted by Aaron Durbin. Remaining unclassified board is: google/pit For which very little info is available publically. Change-Id: I12dfff4c629811a48cfc77be27bdc5081530b8f6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4759 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-19board-status: Add board_info.txt extracted from wiki.Vladimir Serbinenko
board_info.txt is a file to be used by board-status to add some useful info to the generated table like flash chip type. This series is autogenerated from wiki page Supported_Motherboards. Change-Id: Ie2bda900713ef4883134477163320936c84c34f5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4701 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be set with values that are not power of 2. The region programmed as WB cacheable will include all of ROM_SIZE. Side-effects to consider: Memory region below flash may be tagged WRPROT cacheable. As an example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB. Since this can overlap CAR, we add an explicit test and fail on compile should this happen. To work around this problem, one needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and define a smaller region for WB cache. With this change flash regions outside CBFS are also tagged WRPROT cacheable. This covers IFD and ME and sections ChromeOS may use. Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4625 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-03asrock/imb-a180: Configure the 6 COM ports and the keyboardDave Frodin
Change-Id: I66d0715f3be201f8068acd7097e2be49185bee00 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/4574 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-26AMD AGESA: Drop MEM_TRAIN_SEQKyösti Mälkki
This config was for AMD K8 only. Change-Id: Ic1ce60041fef6ddee2dae0e3559fb78f088740af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4556 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includesKyösti Mälkki
Change-Id: Ib3a69e3364418426438f88ba14e5cf744e2414fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4524 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26AMD boards (non-AGESA): Cleanup earlymtrr.c includesKyösti Mälkki
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4523 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-07Correct file permissions.Idwer Vollering
Some files have incorrect/odd permissions, correct them: remove unnecessary +x flags. Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4490 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-05AMD Kabini: fix issue 'S3 fails to suspend after wake up from USB keyboard'Zheng Bao
Propagated from http://review.coreboot.org/3347 http://review.coreboot.org/3374 The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. Both amd/olivehill and asrock/imb-a180 have been validated. Change-Id: I7c26cb07bcd2e62bb792809b67314e5155c6adf6 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4261 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-05AMD Kabini: Add ACPI sleep/wakeup calls for southbridgeZheng Bao
The AML code of PTS and WAK for southbridge are in UINT8 AlibSsdtKB[], Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h. It was integrated into SSDT even it was called by nobody. The source ASL was provided by AGESA for reference, but it has been scrubbed when it was ported to Coreboot. Without the calls, Olive Hill can not wake up if it boots Windows. Both amd/olivehill and asrock/imb-a180 have been validated. Change-Id: Ia7bba29904dbd6f33fdb08bf88bb499005ef561b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4260 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-22AMD f15tn, f16kb: Remove CDIT table and DMI tableWANG Siyuan
On AMD Trinity and Kabini boards errors similar to the following are shown. ASSERTION FAILED: file 'src/mainboard/asrock/imb-a180/agesawrapper.c',line 431 DmiTable:100123f7, AcpiPstatein: 10010129,AcpiSrat:0,AcpiSlit:0, Mce:10010de9,Cmc:10010eab,Alib:1002111c, AcpiIvrs:0 in agesawrapper_amdinitlate agesawrapper_amdinitlate failed: 5 The reason is that on f16kb boards, the CDIT and DMI table are not created. On f15tn boards, only the DMI table is not created. Until the root cause is found, disable the table generation to remove the errors. Thanks to Wei Hu for debugging and reporting this issue on the list [1]. [1] http://www.coreboot.org/pipermail/coreboot/2013-November/076607.html CDIT table is not created Change-Id: I837e3c322bb5331a9b950a72397796a60642c3f3 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/4092 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-11-12AMD Hudson: Move function s3_resume_init_data to southbridgeZheng Bao
Besides the AGESA static settings, the settings in mainboard/buildOpt.c also change the final configuration. We need to make sure the settings in FchParam in resume stage are the same as they were in cold boot stage, otherwise the board can not wake up more than once. Tested on AMD/Olive Hill, AMD/Parmer and ASRock/imb-a180. (USB keyboard doesn't work when board wakes up. It is not introduced by this patch. It needs more debugging.) Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/3932 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2013-10-15ASRock IMB_A180: fix Ubuntu HDMI audio issueWANG Siyuan
Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can resolve this issue. I have tested on Ubuntu 13.04 with latest graphic driver. Change-Id: I09c19b8925eedee03cfb1d8c0831a84e8aeeba4f Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3937 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-10-07AMD hudson yangtze: Fix corruption of a global ramstage variableKyösti Mälkki
A late for loop may reference over the current array allocation and corrupt an unrelated global variable. As a quick fix bumb the size of the array allocation uniformly to 6. We missed these boards for commit 9c7d73ca because the arrays had been renamed. Change-Id: Iff2f2a0090d9302576bc72195d2a3f6fa37ce29a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3954 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-09-27ASRock IMB_A180: fix Windows 7 HDMI audio issueWANG Siyuan
Windows 7 cannot find HDMI audio device because of acpi setting. I have tested on Windows 7. I can play music. Change-Id: I53177ce00b676824a903a3397d69338e8c1a38af Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3936 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-17Fix whitespace leaked into treeKyösti Mälkki
Clean whitespace errors that have gotten past lint-stable-003-whitespace and gerrit review. Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3920 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-11AMD sb800 sb900: Fix corruption of a global ramstage variableKyösti Mälkki
A late for loop may reference over the current array allocation and corrupt an unrelated global variable. As a quick fix bumb the size of the array allocation uniformly to 6. Change-Id: Ib067fdf077e091d13e32cc3a8e4a0b713d19bcc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3914 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-08-27ASRock IMB-A180: Add CODEC initialization tableBruce Griffith
Change-Id: Ic4d191bd34179af707449a15026079da1412ed60 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3886 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
2013-08-27ASRock IMB-A180: Add new AMD Embedded G-Series SOC mainboardWANG Siyuan
Tested on Ubuntu 12.10. S3 is supported. No HD Audio. Mainboard details: http://www.asrock.com/ipc/overview.asp?Model=IMB-A180 Change-Id: I75254194ab5da8e5c61383d8f85aa4e300815637 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3880 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-16Correct spelling of shadow, setting and memoryPaul Menzel
Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3768 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15Include boot_cpu.c for romstage buildsKyösti Mälkki
ROMCC boards were left unmodified. Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-07-10Rename hardwaremain() to main()Stefan Reinauer
... and drop the wrapper on ARMv7 Change-Id: If3ffe953cee9e61d4dcbb38f4e5e2ca74b628ccc Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3639 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-24AMD: Drop empty root_complexKyösti Mälkki
There are no files to build left under AMD nortbridge/x/root_complex directories. For some cases, even the Kconfig file was no longer sourced. Remove all such references and empty files. For devicetree.cb treat component paths with "/root_complex" in them valid even when the directory does not exists. This is because AMD boards us this dummy chip component as the root node in their devicetree.cb. The generated devicetree file static.c remains unchanged. Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3434 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-23AMD boards: routing.asl: Uniformly start `Package()` with capital letterPaul Menzel
In commit Rudolf Marek discovered, that it is not uniformly written. As »ASL names are not case-sensitive and will be converted to upper case.« [2] this change does not have any functional change. The following command was used to create this patch. $ git grep -l 'package()' src/mainboard | xargs sed -i 's,package(),Package(),' [1] http://review.coreboot.org/#/c/3318/ [2] http://www.acpi.info/spec40a.htm (18.2.1 ASL Names) Change-Id: I1784dbc50936a1ef9d4376209a3c324ef1fb85cf Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3516 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17AMD southbridges: Move HAVE_HARD_RESETKyösti Mälkki
All 3 boards with AGESA_HUDSON had HAVE_HARD_RESET with the reset.c file already placed under southbridge/. All 15 boards with CIMX_SBx00 had HAVE_HARD_RESET with functionally identical reset.c file under mainboard/. Move those files under respective southbridge/. Change-Id: Icfda51527ee62e578067a7fc9dcf60bc9860b269 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3486 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-05-30AMD Llano, Brazos boards: Use `sizeof(var)` to get its sizePaul Menzel
Change `sizeof(type) * n`, where n is the number of array elements, to `sizeof(variable)` to directly get the size of the variable (struct, array). Determining the size by counting array elements is error prone and unnecessary. Rudolf Marek’s patch »ASUS F2A85-M: Correct and clean up PCIe config« [1] contains the same change and is ported over. In the commit message Rudolf makes the following comment. »Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR?« Testing on the ASRock E350M1, no regressions were noticed. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I123031b3819a10c9c85577fdca96c70d9c992e87 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3248 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-14AMD Brazos/Trinity boards: PlatformGnbPcie.c: Reserve correct amount of memoryPaul Menzel
In `PlatformGnbPcie.c` AGESA functions are used to reserve memory space to save the PCIe configuration to. This is the With the following definitions in `AGESA.h` $ more src/vendorcode/amd/agesa/f14/AGESA.h […] /// PCIe port descriptor typedef struct { IN UINT32 Flags; /**< Descriptor flags * @li @b Bit31 - last descriptor in complex */ IN PCIe_ENGINE_DATA EngineData; ///< Engine data IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info } PCIe_PORT_DESCRIPTOR; /// DDI descriptor typedef struct { IN UINT32 Flags; /**< Descriptor flags * @li @b Bit31 - last descriptor in complex */ IN PCIe_ENGINE_DATA EngineData; ///< Engine data IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info } PCIe_DDI_DESCRIPTOR; /// PCIe Complex descriptor typedef struct { IN UINT32 Flags; /**< Descriptor flags * @li @b Bit31 - last descriptor in topology */ IN UINT32 SocketId; ///< Socket Id IN PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). IN PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). IN VOID *Reserved; ///< Reserved for future use } PCIe_COMPLEX_DESCRIPTOR; […] memory has to be reserved for the `PCIe_COMPLEX_DESCRIPTOR` and, as two struct members are pointers to arrays with elements of type `PCIe_PORT_DESCRIPTOR` and `PCIe_DDI_DESCRIPTOR`, space for these times the number of array elements have to be reserved: a + b * 5 + c * 2. sizeof(PCIe_COMPLEX_DESCRIPTOR) + sizeof(PCIe_PORT_DESCRIPTOR) * 5 + sizeof(PCIe_DDI_DESCRIPTOR) * 2; But for whatever reason parentheses were put in there making this calculation incorrect and reserving too much memory. (a + b * 5 + c) * 2 So, remove the parentheses to reserve the exact amount of memory needed. The ASRock E350M1 still boots with these changes. No changes were observed as expected. Rudolf Marek made this change as part of his patch »ASUS F2A85-M: Correct and clean up PCIe config« [1]. Factor this hunk out as it affects all AMD Brazos and Trinity based boards. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I32e8c8a3dfc5e87eb119eb17719d612e57e0817a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3239 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-08copy_and_run: drop boot_complete parameterStefan Reinauer
Since this parameter is not used anymore, drop it from all calls to copy_and_run() Change-Id: Ifba25aff4b448c1511e26313fe35007335aa7f7a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3213 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-07asrock/e350m1: reduce default stack sizeStefan Reinauer
The stack used on the ASRock E350M1 is significantly less than what we currently set (64k per core). In fact, we use about half of the default stack size (4k) on core 0 and even less on non BSP cores [1]: $ grep stack coreboot_without_patch_but_monotonic_timer.log CPU1: stack_base 002a0000, stack_end 002afff8 CPU1: stack: 002a0000 - 002b0000, lowest used address 002afda8, stack used: 600 bytes CPU0: stack: 002b0000 - 002c0000, lowest used address 002bf75c, stack used: 2212 bytes Removing the Kconfig variable STACK_SIZE to use the default results in the following numbers of stack usage. $ grep stack coreboot_with_patch.log CPU1: stack_base 00287000, stack_end 00287ff8 CPU1: stack: 00287000 - 00288000, lowest used address 00287da8, stack used: 600 bytes CPU0: stack: 00288000 - 00289000, lowest used address 0028875c, stack used: 2212 bytes [1] http://review.coreboot.org/#/c/3154/ (comment May 2 10:21 AM) Change-Id: Ibdb2102c86094fce3787e3b5a162ca8423de205c Signed-off-by: Stefan Reinauer <reinauer@google.com> Tested-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3209 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-20AMD SB800 based boards: Use `#include <sb_cimx.h>` instead of `"sb_cimx.h"`Paul Menzel
Due to $ more src/southbridge/amd/cimx/sb800/Makefile.inc […] romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c ramstage-y += cfg.c ramstage-y += late.c […] `src/southbridge/amd/cimx/sb800/` is passed with the switch `-I` to the compiler, where it is also going to find the header file `sb_cimx.h`. Therefore use `#include <sb_cimx>` everywhere, which is what some AMD SB800 based boards already do. The only effect is, that the compiler will not needlessly look into directories which do not contain the header file [1]. The following command was used for the replacement. $ git grep -l sb_cimx.h src/mainboard/ | xargs sed -i 's/#include "sb_cimx.h"/#include <sb_cimx.h>/' [1] http://gcc.gnu.org/onlinedocs/cpp/Search-Path.html Change-Id: I96ab34bac1524e6c38c85dfe9d99cb6ef55e6d7c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3118 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-11ASRock DSDT: Split the ASRock DSDTMike Loptien
This is the same split as was done on the Persimmon. Change-Id: I25bd63f23417b7926232f07eaaa7917170af9d60 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3050 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-03ASRock E350M1: Kconfig: Remove `WARNINGS_ARE_ERRORS` to treat warnings as errorsPaul Menzel
Now that the ASRock E350M1 builds without any warnings, remove the config option `WARNINGS_ARE_ERRORS` set to no by default from the file `Kconfig` so warnings are treated as errors to prevent code from being added in the future introducing warnings. Change-Id: Idfecfb1434158969334a4b37972b5fc6fd76e72a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3014 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-02ASRock E350M1: buildOpts.c: Add missing memory related definesPaul Menzel
When building the ASRock E350M1, the following warnings are shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/buildOpts.romstage.o In file included from src/mainboard/asrock/e350m1/buildOpts.c:294:0: src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2071:6: warning: "DDR1333_FREQUENCY" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2071:40: warning: "DDR1866_FREQUENCY" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2089:5: warning: "TIMING_MODE_AUTO" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2089:31: warning: "TIMING_MODE_SPECIFIC" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2113:5: warning: "QUADRANK_UNBUFFERED" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2113:33: warning: "QUADRANK_UNBUFFERED" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2127:5: warning: "POWER_DOWN_BY_CHIP_SELECT" is not defined [-Wundef] src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2127:28: warning: "POWER_DOWN_BY_CHIP_SELECT" is not defined [-Wundef] […] Adding the corresponding defines as done for AMD Persimmon in commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98@gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 addresses the warnings. Change-Id: Id311b2dacdba5f2e6b4d834e43db0310213a35f9 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2962 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-01ASRock E350M1: mptable.c: Remove unused variable `dev`Paul Menzel
When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/mptable.ramstage.o src/mainboard/asrock/e350m1/mptable.c:64:12: warning: unused variable 'dev' [-Wunused-variable] […] Removing the variable `dev` addresses the warning. The same change was done in the following commit for the AMD Persimmon board. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98@gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 Change-Id: I83f4630cb6ab1e4c95d04b4e8423850ed1858e45 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2965 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01ASRock E350M1: mptable.c: Include `cpu/amd/amdfam14.h` for `get_bus_conf`Paul Menzel
When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/mptable.ramstage.o src/mainboard/asrock/e350m1/mptable.c: In function 'smp_write_config_table': src/mainboard/asrock/e350m1/mptable.c:58:3: warning: implicit declaration of function 'get_bus_conf' [-Wimplicit-function-declaration] […] Including the header file `cpu/amd/amdfam14.h` declaring the function addresses this warning. The same change was done in the following commit for the AMD Persimmon board. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98@gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 Change-Id: I7912571fa57f6512b10fc9b5845427fcb6eb50c0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2966 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite`Paul Menzel
When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/mainboard.ramstage.o src/mainboard/asrock/e350m1/mainboard.c: In function 'mainboard_enable': src/mainboard/asrock/e350m1/mainboard.c:63:2: warning: implicit declaration of function 'pm_iowrite' [-Wimplicit-function-declaration] […] This warning was introduced by moving the initialization of the ASF registers using `pm_iowrite` to `mainboard.c` in commit db6c5bfd8bdef4489e7fec533cb2ca8ae6c24cf3 Author: Jens Rottmann <JRottmann@LiPPERTembedded.de> Date: Thu Mar 21 22:21:28 2013 +0100 Asrock E350M1: Use SPD read code from F14 wrapper Reviewed-on: http://review.coreboot.org/2875 and is fixed by including `southbridge/amd/cimx/cimx_util.h` declaring `pm_iowrite`. Note, that the other AMD SB800 based boards seem to use the header file `southbridge/amd/sb800/sb800.h`, so no warning is shown for those. But since the CIMx SB800 code is used, the routines from the CIMx directory are more appropriate to declare these functions. So delete the commented out include line for this header too. Change-Id: I179aad5157c5a91294339a3e7b6c4c1715c6f099 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2957 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-30ASRock E350M1: irq_tables.c: Include `cpu/amd/amdfam14.h` for `get_bus_conf`Paul Menzel
When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/irq_tables.ramstage.o src/mainboard/asrock/e350m1/irq_tables.c: In function 'write_pirq_routing_table': src/mainboard/asrock/e350m1/irq_tables.c:64:2: warning: implicit declaration of function 'get_bus_conf' [-Wimplicit-function-declaration] […] Including the header file `cpu/amd/amdfam14.h` declaring the function addresses this warning. The same change was done in the following commit for the AMD Persimmon board. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98@gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 Change-Id: I40b5735feb7116961ca0c4d6940ec55cdf42d3c6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2956 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-30ASRock E350M1: get_bus_conf.c: Include `agesawrapper.h` for ↵Paul Menzel
`agesawrapper_amdinitlate` When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/get_bus_conf.ramstage.o src/mainboard/asrock/e350m1/get_bus_conf.c: In function 'get_bus_conf': src/mainboard/asrock/e350m1/get_bus_conf.c:82:3: warning: implicit declaration of function 'agesawrapper_amdinitlate' [-Wimplicit-function-declaration] […] Including the header file `agesawrapper.h` declaring the function `agesawrapper_amdinitlate` fixes this warning. All AMD Family 14 based boards already include that header file. For example for the board AMD Persimmon the following patch fixed this warning. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98@gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 Change-Id: I695420b7071e07cb7d4667b2479b9a26ea13723d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2955 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-30ASRock E350M1: PlatformGnbPcie.c: Do not return anything for void return typePaul Menzel
When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/PlatformGnbPcie.romstage.o CC mainboard/asrock/e350m1/agesawrapper.romstage.o CC mainboard/asrock/e350m1/buildOpts.romstage.o src/mainboard/asrock/e350m1/PlatformGnbPcie.c: In function 'OemCustomizeInitEarly': src/mainboard/asrock/e350m1/PlatformGnbPcie.c:131:5: warning: 'return' with a value, in function returning void [enabled by default] […] The function signature is (the return type might not be part of this though [1]), VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) so do not return anything. All other AMD Family 14 boards already have the correct code. For example following commit fixed this for AMD Persimmon. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98@gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 [1] http://cboard.cprogramming.com/cplusplus-programming/117286-what-exactly-function-signature.html Change-Id: Ie60246bd9bb8452efd096e6838d8610f6364a6aa Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2954 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-22Asrock E350M1: Use SPD read code from F14 wrapperJens Rottmann
Changes: - Get rid of the E350M1 mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I08c2aebc62facc14f94400ee1ad188901ba73f19 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2875 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-17ASROCK Fam14 DSDT: Add secondary bus range to PCI0Mike Loptien
Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the Persimmon DSDT. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses. This is the same change as made to Persimmon with change-id I44f22: http://review.coreboot.org/#/c/2592/ Change-Id: I5184df8deb7b5d2e15404d689c16c00493eb01aa Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2736 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-17ASROCK Fam14 DSDT: Remove INI method from AZHD deviceMike Loptien
I am removing the _INI method from the AZHD device because it does not seem to do anything and causes errors in the FWTS[1] (Firmware Test Suite) test 'method'. The INI method performs device specific initialization and is run when OSPM loads a description table. It must only access OperationRegions that have been indicated as available by the _REG (Region) method. We do not have a _REG method and during my testing, I added a REG method but it did not seem to make a difference in the PCI register space. The bit fields defined as NSDI (Disable No Snoop), NSDO (Disable No Snoop Override), and NSEN (Enable No Snoop Request) do not ever get written from their default values. And writing to these bit fields does not seem to be necessary because I did not notice any change in audio functionality. In an effort to clean up as many FWTS errors as possible, I propose removing this method altogether. I have seen no change in operation (audio works with and without this method) and there does not seem to be any change in lspci or dmesg. FWTS information can be found here: [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same change as made to Persimmon in Change-ID If8d86f: http://review.coreboot.org/#/c/2726/ Change-Id: Iae70c3d0af1cdaca31b206ad6daba4d38ee6b780 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-17ASROCK Fam14 DSDT: Add OSC methodMike Loptien
The _OSC method is used to tell the OS what capabilities it can take control over from the firmware. This method is described in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4 inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and returns a Capabilites Buffer the same size as the input Buffer. This Buffer is generally 3 Dwords long consisting of an Errors Dword, a Supported Capabilities Dword, and a Control Dword. The OS will request control of certain capabilities and the firmware must grant or deny control of those features. We do not want to have control over anything so let the OS control as much as it can. The _OSC method is required for PCIe devices and dmesg checks for its existence and issues an error if it is not found. This is the same change made to Persimmon with Change-ID I149428: http://review.coreboot.org/#/c/2684/ Change-Id: I2701d915338294bdade2ad334b22a51db980892e Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-08AMD CIMx SB800 boards: platform_cfg.h: Integrate Kconfig SATA Mode choicePaul Menzel
Currently for Advansus A785E-I, ASRock E350M1 and ASUS M5A88-V despite what is chosen in Kconfig »Chipset« menu item, $ more .config […] # CONFIG_ENABLE_IDE_COMBINED_MODE is not set CONFIG_IDE_COMBINED_MODE=0x1 # CONFIG_SB800_SATA_IDE is not set CONFIG_SB800_SATA_AHCI=y # CONFIG_SB800_SATA_RAID is not set CONFIG_SB800_SATA_MODE=0x2 […] the SATA controller is put into IDE mode. $ lspci -nn | grep SATA 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode] [1002:4390] (rev 40) Commit »sb800: Add sata ahci/raid mode kconfig option« (d4a0e7d0) [1] added the options above to configure the mode using Kconfig and some SB800 boards were adapted already. For example commit »persimmon: sb800 sata mode configure update« (1386fa74) [2] did so for AMD Persimmon. Doing the same by assigning the Kconfig variable to the value in `platform_cfg.h` integrates this with the three remaining boards listed above. The patch is successfully tested with the ASRock E350M1. $ lspci -nn | grep SATA 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] (rev 40) [1] http://review.coreboot.org/225 [2] http://review.coreboot.org/227 Change-Id: I227257e2c8f04f18c27ff00fe62d42e372de67e4 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2610 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-07ASRock E350M1: Let `BiosGnbPcieSlotReset()` return `AGESA_UNSUPPORTED`Paul Menzel
Quoting Jens Rottmann [1]: Nevertheless I still think this whole function is bogus for the E350M1. The function assumes GPIO21 is wired to reset APU PCIe lane 0+1 (PCIe x8, port 4+5 as Coreboot/AGESA calls it), GPIO25 resets lane 2 (PCIe x4) and GPIO02 lane 3. But the E350M1 has PCIe x16 i.e. probably APU lanes 0-3 bundled, completely different layout. They could have chosen GPIO21 to force resets, or 25 - or maybe 50 like on the Persimmon or any other they fancied or - and this is the most probable - none at all. Having BiosGnbPcieSlotReset() toggle some GPIOs without knowing what they do on the E350M1 (if anything at all) is nonsense. In my opinion this whole function should just "return AGESA_UNSUPPORTED" and good riddance. [1] http://review.coreboot.org/#/c/2445/ Change-Id: Iac66da41182e838c7e6925250cc3982adbb3e4ec Reported-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2489 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
2013-03-06ASRock E350M1: mainboard.c: Add declarations for `set_pcie_{,de}reset`Paul Menzel
Since the merg of the ASRock E350M1 port (a649a96e) the compiler warns about the following [1]. mainboard.c:35, GNU Compiler 4 (gcc), Priorität: Normal no previous prototype for 'set_pcie_reset' [-Wmissing-prototypes] mainboard.c:43, GNU Compiler 4 (gcc), Priorität: Normal no previous prototype for 'set_pcie_dereset' [-Wmissing-prototypes] Adding the function prototypes to the beginning of the file as done in commit »Persimmon updates for AMD F14 rev C0« (d7a696d0) addresses the warning. [1] http://qa.coreboot.org/job/coreboot-gerrit/4975/warnings13Result/package.-139448264/file.-1544928473/ [2] http://review.coreboot.org/137 Change-Id: Iad2e62ec37c3a2f749a264974b61ac7c226e9b83 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2590 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-02ASRock E350M1: Remove non-existing PCI devices 12.1 and 13.1Paul Menzel
Looking at the coreboot log […] PCI: 00:12.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it. sb800_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb800_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it. sb800_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled […] and the `lspci -tnvv` output running the proprietary vendor BIOS attached to the Wiki page of the ASRock E350M1 [1][2] -[0000:00]-+-00.0 1022:1510 +-01.0 1002:9802 +-01.1 1002:1314 +-04.0-[01]-- +-11.0 1002:4391 +-12.0 1002:4397 +-12.2 1002:4396 +-13.0 1002:4397 +-13.2 1002:4396 […] both PCI devices do not exist, so remove them from `devicetree.cb`. Commit 48918f7 [3] Persimmon, Inagua: PCI devs 12.1, 13.1 (USB) don't exist, but 14.6 (GEC) does did the same for AMD Inagua and AMD Persimmon. [1] http://www.coreboot.org/ASRock_E350M1 [2] http://www.coreboot.org/File:ASRock_E350M1_info_dump.tar.bz2 [3] http://review.coreboot.org/2463 Change-Id: Ief6de1bda093d1f29d5925985e5c3839cdded537 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2536 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
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