coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2010-12-08	Move "select CACHE_AS_RAM" lines from boards into CPU socket.	Uwe Hermann
2010-12-08	second round name simplification. drop the <component>_ prefix.	stepan
2010-12-08	first round name simplification. drop the <component>_ prefix.	stepan
2010-11-24	S3 support for ASUS M2V	Tobias Diedrich
2010-11-22	1) wraps the s3 parts of chipset code/memory init code with if CONFIG_HAVE_AC...	Rudolf Marek
2010-11-21	Simplify a few code chunks, fix whitespace and indentation.	Uwe Hermann
2010-11-21	Drop excessive whitespace randomly sprinkled in romstage.c files.	Uwe Hermann
2010-11-21	Use DIMM0 et al in lots more places instead of hardocding values.	Uwe Hermann
2010-11-17	Dynamically generate PNP0C02 mainboard resources in SSDT	Tobias Diedrich
2010-11-17	The only southbridge having a pirq_assign_irqs function (needed for	Tobias Diedrich
2010-11-16	Forgot to remove one set of SET_FIDVID defines	Patrick Georgi
2010-11-16	Move the SET_FIDVID* family of configuration options to Kconfig and	Patrick Georgi
2010-11-14	Return 0, (as for 40pin cable if SB not found)	Rudolf Marek
2010-11-14	Move cable detect logic to a weak function in vt8237r_ide.c and add	Tobias Diedrich
2010-11-12	mainboard/asus/m2v: Set DDR2 voltage to 1.8V	Tobias Diedrich
2010-11-10	Use the new mptable_write_buses() on the ASUS M2V.	Tobias Diedrich
2010-11-10	Add mptable for ASUS M2V.	Tobias Diedrich
2010-11-09	Add acpi tables and dsdt.	Tobias Diedrich
2010-11-09	Add pirq table for ASUS M2V.	Tobias Diedrich
2010-11-07	Should be part of 6044. I forgot to add the directory :/	Tobias Diedrich