coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2016-03-10	northbridge/intel/i440bx: Unify UDELAY selection	Stefan Reinauer
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-05-03	Move ARCH_* from board/Kconfig to cpu or soc Kconfig.	Furquan Shaikh
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-05-01	Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boards	Stefan Reinauer
2010-10-30	Mptable related fixes for ASUS P2B-DS.	Uwe Hermann
2010-10-06	Convert all Intel 440BX boards to Cache-as-RAM (CAR).	Uwe Hermann
2010-08-30	Restructured all vendors' Kconfig files to no longer source the boards'	Jens Rottmann
2010-07-06	Re-integrate "USE_OPTION_TABLE" code.	Edwin Beasant
2010-05-14	license header fixes	Nils Jacobs
2010-03-13	Use CPU_INTEL_SLOT_1 for Slot 1 boards (trivial).	Uwe Hermann
2010-03-13	Add SDRAMPWR_4DIMM Kconfig option (not user-visible in menuconfig).	Keith Hui
2010-02-09	Move all the copies of the romstage.inc rule to	Patrick Georgi
2010-01-25	Align several kconfig options to match newconfig:	Patrick Georgi
2010-01-18	Move all IOAPIC selection to southbridges, and remove them	Patrick Georgi
2009-10-16	Set default ROM sizes per-board to match the ROM chip that came	Uwe Hermann
2009-10-06	Use	Uwe Hermann
2009-10-05	PCI_ROM_RUN and CONSOLE_VGA are global options in Kconfig and	Uwe Hermann
2009-10-03	Remove duplicate and not too useful Kconfig board comments as	Uwe Hermann
2009-08-26	Add kconfig support for all missing Intel 440BX based boards.	Uwe Hermann