coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-06-06	mb//: Add a few VBT files	Arthur Heymans
2018-01-26	mb///cmos.layout: Fix the values for the console level	Arthur Heymans
2018-01-17	cpu/intel/speedstep: Fix the PNOT ACPI method	Arthur Heymans
2018-01-14	mb/asus/p5gc-mx/romstage.c: Remove unused IO decode ranges	Arthur Heymans
2018-01-14	mb///romstage.c: Clean up targets with i82801gx	Arthur Heymans
2017-12-11	intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c	Elyes HAOUAS
2017-09-23	mb//: Remove rtc nvram configurable baud rate	Arthur Heymans
2017-07-24	Update files with no newline at the end	Martin Roth
2017-07-24	Fix files with multiple newlines at the end.	Martin Roth
2017-07-12	mb/asus/p5gc-mx: Implement resume from S3 support	Arthur Heymans
2017-05-11	nb/intel/i945: Define and use a default MMCONF_BASE_ADDRESS	Arthur Heymans
2017-04-07	nb/intel/i945: Move INTEL_EDID	Patrick Rudolph
2017-01-06	mb/asus/p5gc-mx: Use common/gpio.h	Arthur Heymans
2017-01-04	intel/i945 boards: Add romstage time stamps	Paul Menzel
2017-01-03	mb/asus/p5gc-mx: Remove extra BSEL strap check	Arthur Heymans
2016-12-28	mb/asus/p5gc-mx: Fix and complete SIO devicetree options	Arthur Heymans
2016-12-22	mb/asus/p5gc-mx: Add mainboard	Arthur Heymans