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path: root/src/mainboard/asus/p5qc/romstage.c
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2019-11-15nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15nb/intel/x4x: Move boilerplate romstage to a common locationArthur Heymans
This adds 3 mb romstage callbacks: - void mb_lpc_setup(void) to be used to set up the superio - void mb_get_spd_map(u8 spd_map[4]) to get I2C addresses of SPDs - (optional)mb_pre_raminit_setup(int s3_resume) to set up mainboard specific things before the raminit. Change-Id: Ic3b838856b3076ed05eeeea7c0656c2078462272 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36758 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14sb/intel/i82801jx: Move early sb init to a common placeArthur Heymans
Setting southbridge GPIO is now done after console init, which should be fine. This code is partially copied from i82801ix. Change-Id: I51dd30de4a82898b0f1d8c4308e8de4a00d1b7aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36756 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12sb/intel/i82801jx: Add common code for LPC decodeArthur Heymans
Change-Id: Id706da33f06ceeec39ea50301130770226f0474e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-11mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'Elyes HAOUAS
Change-Id: I82f1d4325ea87585137fa81567aa82b80454c704 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-13sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
Use common code to detect ACPI S3. Untested. Change-Id: I2264c087b317f70506817b5458295a17e83b1efc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32038 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-10mb: Move timestamp_add_now to northbridge x4xElyes HAOUAS
Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-09cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans
The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-10-15mb/asus/p5qc: Add mainboardArthur Heymans
SeaBIOS does not seem to like the Marvel IDE controller, so disabled SeaBIOS support for ATA. It works fine in Linux afterwards. Working: - SATA on southbridge port - SATA on marvel IDE controller ports (only in Linux) - USB - COM1 - PS2 Keyboard - DDR2 DIMMs - PCIe x16 PEG port - PCI port - NIC (needs a driver to set macaddress) - S3 resume Not working: - SeaBIOS with ATA support (long timeout marvel controller so disabled) - DDR3 fails because the proper clock signal does not get enabled. Even when fixing this it fails later or during memtest, so it should be considered unsupported for now Untested: - PCIe x1 ports (expected to work) - sound (expected to work) TODO: add documentation Change-Id: I4a81940707566776bd048904ca1387fea741fece Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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