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2015-11-12mainboard/asus/kgpe-d16: Add sata_alpm CMOS optionTimothy Pearson
Change-Id: I2f2658eb8b3142c86fef4ee50792f51954686cca Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12409 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12mainboard/asus/kgpe-d16: Add dimm_spd_checksum CMOS optionTimothy Pearson
Change-Id: I12323d76ab90f643f4dd4351d7e99824ec24f9be Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12408 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-12mainboard/asus/kgpe-d16: Add missing IRQ routing for PIKE cardTimothy Pearson
Change-Id: I6eba36dad71a2a2713181382484dc0e0976e1dad Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11988 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11mainboard/asus/kgpe-d16: Add maximum_p_state_limit CMOS optionTimothy Pearson
Change-Id: I9a7049fd5601da10a954e02427ad59189fa93fa9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12407 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-11-11mainboard/asus/kgpe-d16: Set SP5100 subtypeTimothy Pearson
Change-Id: If839fd71ed12c1fe27aeab374e242a6855737f5d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11994 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS optionTimothy Pearson
Change-Id: If7b6062fd4df16ae2864b5d9adfdd19c4356691c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12400 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-11cpu/amd: Add CC6 supportTimothy Pearson
This patch adds CC6 power save support to the AMD Family 15h support code. As CC6 is a complex power saving state that relies heavily on CPU, northbridge, and southbridge cooperation, this patch alters significant amounts of code throughout the tree simultaneously. Allowing the CPU to enter CC6 allows the second level of turbo boost to be reached, and also provides significant power savings when the system is idle due to the complete core shutdown. Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11979 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11asus/k8v-x: Add more subsystem IDs to device treeUrja Rannikko
This is an attempt at better compatibility with driver matching etc. Change-Id: I26eccbe17a31ba2042d0fe1bb424d9f380c0a82e Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: http://review.coreboot.org/12351 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11asus/k8v-x: Add PIRQ tables to init PCI IRQ configUrja Rannikko
Pulled getpir from the attic and used data provided by it to create the table a bit more programmatically and added the AGP slot so the video card is given an IRQ Change-Id: Id3dc1a77ac6382405f5f36707994287e84e1168b Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: http://review.coreboot.org/12350 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11mainboard/asus/kgpe-d16: Enable CC6Timothy Pearson
Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11978 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-11-11amd/amdmct/mct_ddr3: Use training values from previous boot if possibleTimothy Pearson
DRAM training accounts for most of the romstage startup time, yet if the hardware configuration has not changed from the previous boot the previously discovered training values are still valid. Use them if the DIMM configuration has not changed since the last boot. The SPD values of all installed DIMMs are hashed and stored in the S3 resume data area of the main system Flash device. If a DIMM is changed the hash will almost certainly change as well, forcing retraining on next boot. Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11976 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11mainboard/asus/kgpe-d16: Set correct supported SATA port countTimothy Pearson
Change-Id: Ia5c00f07de81d409e6215cc0944d64d00e47b795 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12401 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-11southbridge/amd/sb700: Indicate iSATA/eSATA port typeTimothy Pearson
Change-Id: I8ee757d07c82c151b36def6b709163ff144d244f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11984 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11mainboard/asus/kgpe-d16: Properly initialize SB700 SATA PHYsTimothy Pearson
Change-Id: I5323462dcb8a4e84786be38cc85070eb48d4a31d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11982 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-10mainboard/**/irq_tables.c: Remove reference to getpirPatrick Georgi
The obsolete and removed getpir utility remarked in its output that the data is autogenerated. The tool was removed because it wasn't very reliable, so there's no need to point that anymore. Change-Id: I5d624931ba7872b1fefa8fa3c270ae7367e069fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12354 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-10asus/kgpe-d16: fix DIMMSetVoltagesFelix Held
The RAM voltages can be set per socket, which contains two nodes. Only reset the allowed voltages per socket before processing a new socket and not after every node. Change-Id: Ia0e47676c7a3eebd56a17ab6de0e9690bf8cf703 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/12297 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-11-10asus/k8v-x: set superio ROM ctrl reg to enable writesUrja Rannikko
This is required for flashrom to work... Change-Id: Icc0a52e0ca103c897d96fa8f3cf83b30780c7b49 Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: http://review.coreboot.org/12349 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10mainboard: Remove empty mainboard.c filesPaul Menzel
All the deleted mainboard files contain no code besides some print statements denoting, that the init is executed. If such statements are desired, this should be done in common code so it does not have to be added to each mainboard. Therefore, also delete files with just print statements. Change-Id: I379e4b1e1b1725648c6231bc6954ac3cc655a596 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/12355 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-09mainboard/asus/kgpe-d16: Add initial Family 15h CPU supportTimothy Pearson
Change-Id: I76f74ed4ae383f8b1f57eaaa2e025035002430f2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11967 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-05mainboard: Remove last_boot NVRAM optionTimothy Pearson
The last_boot NVRAM option was deprecated and removed in commit 3bfd7cc6. Remove the last_boot option from all affected mainboards to eliminate user confusion. Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12316 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-11-04mainboard/asus: Increase reboot count on boards with recovery jumperTimothy Pearson
On server boards with a recovery jumper, having the fallback path less sensitive to power fluctuations or BMC issues makes sense. Increase the maximum number of boot attempts before automatic fallback to 10 on these boards. Change-Id: Iabe0b0cbf332686db8e9380a8b65a1477173599c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12320 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
TEST: Booted ASUS KGPE-D16 with single Opteron 6380 * Unbuffered DDR3 DIMMs tested and working * Suspend to RAM (S3) tested and working Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02cpu/amd: Move model_10xxx to family_10h-family_15hTimothy Pearson
Change-Id: I34501d3fc68b71db7781dad11d5b883868932a60 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11965 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02mainboard/asus/kgpe-d16: Set DDR3 memory voltage based on SPD dataTimothy Pearson
Change-Id: I21777283ce0fd3c607951204a63ff67dc656c8cc Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11956 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02mainboard/asus/kfsn4-dre_k8: Fix ramstage using Family 10h structsTimothy Pearson
Several ramstage files were inadvertently using Family 10h-specfic structures, causing unstable operation. Use the K8-specific structures instead. Change-Id: I64066dfdca83557393499b77726051e25b814381 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12290 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-31mainboard/asus/kgpe-d16: Add initial Suspend to RAM (S3) supportTimothy Pearson
Change-Id: I7da84b064287a445fd75a947e2f96ce1ae30d3de Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11954 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package supportTimothy Pearson
The existing KFSN4-DRE support hung during ramstage while initializing AP #3 if a second CPU package was installed. After analyzing the Sun Ultra 40 M2 support code it became apparent that the K8 code cannot function correctly if sequential RAM training is disabled, and that there were a few other missing calls. This patch adds the missing calls, adjust the CAR space to an appropriate level, and explicitly defines the link numbers and connections in devicetree.cb TEST: Booted ASUS KFSN4-DRE with 2x Opteron 8222 installed. Change-Id: I96178b7367b0c13de5c9d5d90d032fb0c53639c2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12285 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-10-30AMD mainboards: Fix 64bit BiosCallOuts.cStefan Reinauer
Change-Id: I0f3297dff47dfb44da034ac6f305dcf1981b9de1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11080 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30mainboard/asus/m2n-e|msi/ms9282: Clean up FIDVID mistakesTimothy Pearson
These two mainboards contained trivial mistakes related to FIDVID that broke build when FIDVID was enabled. Change-Id: Ie7bec77f26ec37eada21308984db4a9fd7a1866f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12226 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30mainboard: Add initial K8-compatible version of the KFSN4-DRETimothy Pearson
This is a clone of the original Family 10h-compatible ASUS KFSN4-DRE board, modified for basic K8 support to allow for future K8 Socket F Opteron testing. TEST: Booted KFSN4-DRE with 1 Opteron 8222 processor KNOWN ISSUES: * Second CPU package fails to initialize AP This prevents use of a secondary CPU package * Second memory channel of at least CPU package #0 does not function (crash at CAR handoff) Change-Id: I591725babe685fa50a0d7473b17005fbd258056e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12212 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-29mainboard/asus/kgpe-d16: Add nvram option to enable/disable IEEE 1394Timothy Pearson
Change-Id: I4f0f6c1cb1fad5b65f196dc6b443252a0ecc70a1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11947 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-10-29mainboard/asus/kgpe-d16: Properly configure SR5690 southbridge PIKE slotTimothy Pearson
Change-Id: I2f1373905ffd6460ac3c7c21738e2e2a9aa2e463 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11992 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-10-29mainboard: Convert #ifdef to IS_ENABLED in get_bus_conf.cTimothy Pearson
Change-Id: I254e9e9e65519edcf4d3f1ecc385af16d18c2367 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12208 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-28mainboard/asus/kgpe-d16: Add initial support for the KGPE-D16Timothy Pearson
As of this commit S3 suspend does not work on any K10 boards, including this board. Change-Id: Idd3971422fb2473bff7c60fe8d8161d6e20808ed Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11946 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-27asus/f2a85-m: Activate IOMMU supportRudolf Marek
Activate the IOMMU support for the Asus F2A85-M. Add the device to `devicetree.cb`. $ lspci -s 0.2 […] 00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit $ dmesg […] [ 0.000000] ACPI: IVRS 00000000bf144e10 00070 (v02 AMD AMDIOMMU 00000001 AMD 00000000) [ 0.000000] ACPI: SSDT 00000000bf144e80 0051F (v02 AMD ALIB 00000001 MSFT 04000000) [ 0.000000] ACPI: SSDT 00000000bf1453a0 006B2 (v01 AMD POWERNOW 00000001 AMD 00000001) [ 0.000000] ACPI: SSDT 00000000bf145a52 00045 (v02 CORE COREBOOT 0000002A CORE 0000002A) […] Linux 3.10 reported several IO page faults, which could never be explained and which the vendor firmware did not. These errors couldn’t be reproduced with Linux 3.18 by Damien Zammit. Change-Id: I0aa530be17d31656e65db6113343f2ea7008b843 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/3517 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-24amd/acpi: Clean up SMBus references.Tobias Diedrich
Replace the AMD SMBus section with the equivalent SB800 smbus.asl include or remove already commented-out sections. Verified by running the cpp preprocessor over the DSDTs and diffing the results against this patch. The only change is in src/mainboard/siemens/sitemp_g1p1/dsdt.asl, where someone added RADD and SADD to the OpRegion, but those are unused, so removing them is fine. Change-Id: I074c8a1ed1c9a944d4988752bd0fc42c199c766c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10618 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
While the romstage code flow is not consistent across all mainboards/chipsets there is only one way of running ramstage from romstage -- run_ramstage(). Move the timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. TS_END_ROMSTAGE still present in timestamp table. Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11700 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-23AMD Kconfig: Remove QRANK_DIMM_SUPPORT from unsupported platformsMartin Roth
The AMD K8 northbridge uses the Kconfig symbol QRANK_DIMM_SUPPORT, but the symbol was used on a number of Family 10 boards as well. AMD Family 10 doesn't use this Kconfig symbol for anything. I verified that the symbol wasn't used actually getting used in any of these platforms. Fixes Kconfig warnings for these 19 mainboards: warning: (BOARD_SPECIFIC_OPTIONS...) selects QRANK_DIMM_SUPPORT which has unmet direct dependencies (NORTHBRIDGE_AMD_AMDK8) Change-Id: I454992a4975566fd6439a21f5a800d0cfa1b4d3b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11300 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-07-23nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10hJonathan A. Kollasch
Based on the observations that AMD Fam10h with both Nvidia CK804 (Asus KFSN4-DRE) and MCP55 (Sun Ultra 40 M2) need to avoid adjusting the LPC bridge register 0x78 (particularly the 0x7b byte) to get to ramstage: Assume that there's something about this register that adjusting it the way we do for K8 is something that can/should be universally avoided on all Fam10h systems with these chipsets. Change-Id: I1eceeb20ecaefef4c61c11e19d1f5a59f91a0a2f Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10984 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-07-14azalia: fix up and clean up shrinkage of boilerplate codeJonathan A. Kollasch
Should fix regression in HDA verb setup on nvidia mcp55 and intel sch southbridges. The mcp55 code could not find the mainboard's verb table because the table was not even being compiled in. The sch boards appeared to have the same issue. Intel broadwell and fsp_bd82x6x seemed to have not gotten the boilerplate shrink, so apply it to those too. Followup-to: Ib3e09644c0ee71aacb067adaa85653d151b52078 (azalia: Shrink boilerplate) Change-Id: If7aae69f5171db67055ffe220bdff392caaa5d9f Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10826 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-27mainboard/asus/kfsn4-dre: Enable VGA supportTimothy Pearson
The ASUS KFSN4-DRE has full native VGA support, enable support for the VGA device by default in the Kconfig file. Change-Id: I09fc8845a30f26ca49f3547812f9784621ff4b5e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10673 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-06-24Kconfig: Get rid of obsolete symbolsMartin Roth
CAR_MIGRATION was removed in commit: cbf5bdfe - CBMEM: Always select CAR_MIGRATION ALT_CBFS_LOAD_PAYLOAD was removed in commit: cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD MARK_GRAPHICS_MEM_WRCOMB was removed in commit: 30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB. EXTERNAL_MRC_BLOB was removed in commit: 0aede118 - Drop unused EXTERNAL_MRC_BLOB CACHE_ROM is only in Google's codebase. LID_SWITCH is only in Google's codebase. DEFAULT_POST_DEVICE_LPC is only in Sage's codebase. ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used. HUDSON_NOT_LEGACY_FREE never existed as far as I can tell. MAINBOARD_DO_EDID never existed as far as I can tell. Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10616 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-10PCI subsystem: Drop PCI_64BIT_PREF_MEM optionKyösti Mälkki
No board in the tree selects this and it looks like the implementation was done at chipset level while it should be part of PCI subsystem. When enabled, at least AMD K8 and f14, f15tn and f16kb fail build test. Feature of placing prefetchable PCI memory above 4GB may not work if there is any 32-bit only prefetchable PCI BARs in the system. Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8705 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-08Remove empty lines at end of fileElyes HAOUAS
Used command line to remove empty lines at end of file: find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \; Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/10446 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-05AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0Kyösti Mälkki
If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus is the first to scan and it will be assigned with bus number 0. If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range of bus numbers instead of assigning consecutive numbers across all the links. All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge. Follow-up can easily drop this if we find this is dictated by architecture. Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8366 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-24AGESA binaryPI boards: Drop annoying commentaryKyösti Mälkki
Same comments were already removed for the latest board, the amd/lamar. Change-Id: Ie244f838409c567c11f7444c9cf17de72e49dbb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10283 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-23AGESA fam15x fam16x: Remove HAVE_ACPI_RESUMEKyösti Mälkki
Implementation corrupts low-memory on S3 resume path, rendering OS unstable. AMD was never able to pinpoint a revision that did not have the issue. Change-Id: I9656ac1bfe1412775a6152b9f995c4d4ebf57159 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10285 Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>