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Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Only some mainboard vendors have a prompt for this option. Let's be fair
and give this ability to everyone.
Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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They are downright useless and result in ACPI errors. So, burn them.
Also, do a minor update to autoport's README about these values.
Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'.
Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2
Signed-off-by: Ivan Vatlin <jenrus@tuta.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Iba39673a81f235204d6ae9fe9e18239e5b81b17f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I3c63ca745bf10ec0b0c4cef898db3f7ebfee5bde
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38364
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=boot PC Engines apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I3598f548c2d122906fda09c85b5a1c82b0da993b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38255
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib94ce73eb22c5b4b489dbd871279e8cd9a7010a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I4a324dcebcd53439206205e64c5bbb7c6eac4fb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Set up the proper IRQ routing for OHCI/EHCI devices which appear if
XHCI controller is disabled (CONFIG_HUDSON_XHCI_ENABLE is not set).
Now both "USB 3.0" ports are working fine at OHCI/EHCI "USB 2.0" mode.
They also work fine if XHCI controller is enabled.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I50a773eeab890627abc963e0a61f781d1cea3259
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Use lowercase for hex constants, remove registers that default to zero
already and drop outdated comment about AHCI mode.
Change-Id: I6833462ea11e988eaab7913cf98853cebe4c7a9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Align comments, and make PCIe port comments consistent.
Change-Id: Id39337236deff7721183e749a6b63aadaa036b2f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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They default to zero already. Moreover, the comment about AHCI mode no
longer applies, as it was made the default mode.
Change-Id: Ife99a79df0289c6db87510ed917438bf47b7f6ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Use lowercase for hex constants and align some comments.
Change-Id: I418ed29dfbc90feb591a2b30e994d9b3e6176f86
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Use lowercase for hex constants, inline a lone `end` and align a
comment.
Change-Id: Ibf3882dd134d33611138c2a9f89a3b2b37c136b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Replace a bunch of spaces with tabs, put host bridge and friends above
southbridge, fix "TPM Module" (Trusted Platform Module Module) and add
some empty lines to help the reader.
Change-Id: I3a89893f943057ef7a4f973eaa65dba259e8a49d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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They default to zero already.
Change-Id: I5c99043f16bc65de952afa0ce8d40bf947bfee15
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This touches several mainboards. Replace the macro with C functions.
The presence of bootblock.c is assumed.
Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ib45c6372df6068ab041a055dad8bacf597717ba2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.
Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The majority of Socket AM1 APUs [1] - three out of five - have the integrated
VGA with 1002,9830 ID, while only one Sempron has 1002,9836. Since VGA_BIOS_ID
is already defined in fam16kb Kconfig as 1002,9830 ID, drop the value here.
[1] https://en.wikipedia.org/wiki/List_of_AMD_accelerated_processing_units#%22Kabini%22_(2013,_SoC)
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33777
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie8b9df7a64b45167de542182f3dfe6b320b9f2e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Denary, also known as "decimal" or "base 10," is the standard
number system used around the world. Therefore, make use of it.
Change-Id: I7f2937bb7715e0769db3be8cb30d305f9d78b6f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Remove commented-out entries in dsdt.asl, and then remove files that do
not get built.
Change-Id: I579e7ffbc2d6596fd7ffe6863ff3b3fb14b0ade6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already. See
* src/southbridge/intel/*/lpc.c
Change-Id: I5228f2cdc94df722ffa687c45b4e4fd25e82df82
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The gnvs structure was zeroed out before calling acpi_create_gnvs(...)
in the following files:
* src/southbridge/intel/*/lpc.c
Change-Id: Id7755b1e4b8f5cb8abd1f411b5dc174b6beee21c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37956
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Switching was done by moving a SIO configuration and
the clocks setup from 'romstage.c' to 'bootblock.c',
following the example of change CB:37719 (fc749b2).
TEST=Boots into Artix Linux 2019 without a problem.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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It provides no useful information, so it might as well vanish.
Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Change-Id: I5791fddec8b2387df5979adbb1a0fa64c5dd23ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Change-Id: I4dcdcb734e20830ac97d4a826de61017afc6ee67
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I4cd9d22d2105c270a3d1e8a0be40b594c7c8b226
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37687
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I14d3579f232b1dcc95b4e0653520686965dbe727
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Also, don't define the default as this results in spurious lines in the
.config.
TEST: Build all boards with where config.h differed with
BUILD_TIMELESS=1 and remained the same
Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31316
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per the 4.11 release requirement, C_ENVIRONMENT_BOOTBLOCK=y
is a mandatory feature, which most AGESA and binaryPI boards lack.
Disable such platforms from the build for the time being.
The Kconfig symbol has been flipped, ROMCC_BOOTBLOCK=n is the
same mandated feature as C_ENVIRONMENT_BOOTBLOCK=y.
If a platform does not reach ROMCC_BOOTBLOCK=n within a
reasonable timeframe both the mainboard and the respective
unused platform support code will get removed.
Change-Id: I7fceb0370f7f4f5f52080277c5d21615d3ab3454
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37727
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These entries have no functional purpose, followup work will
disallow chip entries that do not link in the respective
driver.
Change-Id: Ieab695022d0dd2f2671f9058db97bdd6fb29a10d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ibe2d92990d0074266aa05ada749e9dad55e609a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Denary, also known as "decimal" or "base 10," is the standard
number system used around the world. Therefore, make use of it.
Change-Id: Ia22705d7629a322292cfd557add9cfadc649c16c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37537
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCIe root port clock gate is already enabled at i945/early_init.c
Also fix comments when only PCIe root port is enabled.
Change-Id: Ica38529dbdd5cc51b19b426999a1d9f0b678b4f5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37576
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Because the function is implemented in C, post_code() calls
from cache_as_ram.S and other early assembly entry files may
not currently work for cold boots. Assembly implementation
needs to follow one day.
This effectively removes PORT80 routing from boards with
ROMCC_BOOTBLOCK.
Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Change-Id: I934830c09f7996e8f5aae5d5abe9fb6014fb478d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
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Allows boards to be transformed to C env bootblock one
at a time.
Change-Id: I1cc1910a8bfb6b3495593979cbf7194b0d82c8e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37345
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kconfig became stricter on what it accepts, so accomodate before
updating to a new release.
Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The generic PCH code already sets up a superset of these decodings.
Change-Id: I90bca37c46b89c35f323225fc3c087f1630397e4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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There is some overlap between romstage and bootblock.
LPC setup and BAR initialization is now done twice.
The rationale is that the romstage should not depend too
much on the bootblock, since it can reside in a RO fmap
region.
Enabling the console will be done in a followup patch.
Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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