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Mimicking change I7037308d2, always compile mdelay for romstage.
The boards that #included delay.c in the romstage now rely on the linker
instead, which is a desirable cleanup.
Change-Id: I7e5169ec94e5417536e967194e8eab67381e7c98
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13115
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I93687efc5405359286d3197f0e59ec3b118c5100
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12809
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I8f6226d3e74ac5c7f29f708128a7502ced1287bf
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12062
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Iac1adbeacdcded7faff2443b78a491cbb8a90fe8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12628
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The newer versions of IASL are unhappy when an operator
has the same object as both source and destination.
The warning can be completely disabled with a command
line argument, but in general, I'd really rather not
just disable warnings.
The bits in this register are write 1 to clear, so reading and
writing the same register is what we want to do. Instead, store
it in a temporary register then write it in a second operation.
Fixes warning:
dsdt.aml 1396: Store(PWST, PWST)
Warning 3023 - ^ Duplicate value in list
(Source is the same as Target)
Change-Id: I52d73d4431db237be83016d67cd397f31b53d9c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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According to the ACPI Spec for CondRefOf, the result argument is
optional. In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL. Since it's
an optional argument, just remove it.
dsdt.aml 22: if(CondRefOf(\_OSI,Local1))
Warning 3144 - ^
Method Local is set but never used (Local1)
Change-Id: I07f49ac5a3708838d1c4a7216dfb11acc415c881
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The existing code incorrectly used standard PCI access
calls in the bootblock. Use the I/O PCI access calls
as the normal PCI access mechanisms have not yet been
set up.
Also ensure the recovery jumper GPIO has been set to
input mode before reading it.
Change-Id: Id626d01526427004b2404e4d9b44d7c987d172d1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12651
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12067
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The CPU <--> CPU HT wiring on this board has only been validated
to 2.6GHz. While higher frequencies appear to function initially,
and in fact function when only one CPU package is installed, dual
CPU package systems will lock up after around 6 - 12 hours of uptime
due to presumed HT link errors at the higher (>= 2.8GHz) HT clocks.
If applications are not being used that stress the coherent fabric,
then the uptime before hang may be much longer. Users attempting
to overclock the HT links are advised to "burn in test" the HT links
by running memtester locked to a node with no local memory installed.
Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12064
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I9a00bdbcd47804b6d83c0231cd515773d02ff951
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12527
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I45b04e8fbdfc65603e1057f7b0e5a13d073fe348
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12048
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add options to control cache partitioning and overall memory
performance via nvram.
Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ia24102e164eb5753ade3f9b5ab21eba2fa60836b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12046
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I2083d0c5653515c27d4626c62a6499b850f7547b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12044
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Certain older Opteron processors use a higher (+1.2V) northbridge
voltage. The existing code assumed the use of +1.1V northbridge
voltages and threw an alert when the older Opterons were installed.
Update the permissible NB voltage range to include both the 1.1V
and 1.2V Opteron processors.
Change-Id: I35c90f37d180f59c53d0d2bf3ff0eaf985b26da3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12027
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Ibefc9dc2e1e0267389eb8d716408bae6026ce084
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12024
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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This fixes Family 15h multiple package support; the previous code
hung in CAR setup and romstage when more than one CPU package was
installed for a variety of loosely related reasons.
TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors
and several different RDIMM configurations.
Change-Id: I171197c90f72d3496a385465937b7666cbf7e308
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12020
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: I2f2658eb8b3142c86fef4ee50792f51954686cca
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12409
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I12323d76ab90f643f4dd4351d7e99824ec24f9be
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12408
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I6eba36dad71a2a2713181382484dc0e0976e1dad
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11988
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I9a7049fd5601da10a954e02427ad59189fa93fa9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12407
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Change-Id: If839fd71ed12c1fe27aeab374e242a6855737f5d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11994
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: If7b6062fd4df16ae2864b5d9adfdd19c4356691c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12400
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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This patch adds CC6 power save support to the AMD Family 15h
support code. As CC6 is a complex power saving state that
relies heavily on CPU, northbridge, and southbridge cooperation,
this patch alters significant amounts of code throughout the
tree simultaneously.
Allowing the CPU to enter CC6 allows the second level of turbo
boost to be reached, and also provides significant power savings
when the system is idle due to the complete core shutdown.
Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11979
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is an attempt at better compatibility with driver matching etc.
Change-Id: I26eccbe17a31ba2042d0fe1bb424d9f380c0a82e
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12351
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Pulled getpir from the attic and used data provided by it
to create the table a bit more programmatically and
added the AGP slot so the video card is given an IRQ
Change-Id: Id3dc1a77ac6382405f5f36707994287e84e1168b
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12350
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11978
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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DRAM training accounts for most of the romstage startup time, yet
if the hardware configuration has not changed from the previous boot
the previously discovered training values are still valid. Use them
if the DIMM configuration has not changed since the last boot.
The SPD values of all installed DIMMs are hashed and stored in the S3
resume data area of the main system Flash device. If a DIMM is changed
the hash will almost certainly change as well, forcing retraining on next
boot.
Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11976
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: Ia5c00f07de81d409e6215cc0944d64d00e47b795
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12401
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Change-Id: I8ee757d07c82c151b36def6b709163ff144d244f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11984
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I5323462dcb8a4e84786be38cc85070eb48d4a31d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11982
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The obsolete and removed getpir utility remarked in its output that the
data is autogenerated. The tool was removed because it wasn't very
reliable, so there's no need to point that anymore.
Change-Id: I5d624931ba7872b1fefa8fa3c270ae7367e069fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12354
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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The RAM voltages can be set per socket, which contains two nodes.
Only reset the allowed voltages per socket before processing a new socket and
not after every node.
Change-Id: Ia0e47676c7a3eebd56a17ab6de0e9690bf8cf703
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12297
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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This is required for flashrom to work...
Change-Id: Icc0a52e0ca103c897d96fa8f3cf83b30780c7b49
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12349
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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All the deleted mainboard files contain no code besides some print
statements denoting, that the init is executed.
If such statements are desired, this should be done in common code so it
does not have to be added to each mainboard.
Therefore, also delete files with just print statements.
Change-Id: I379e4b1e1b1725648c6231bc6954ac3cc655a596
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12355
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I76f74ed4ae383f8b1f57eaaa2e025035002430f2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11967
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The last_boot NVRAM option was deprecated and removed in
commit 3bfd7cc6. Remove the last_boot option from all
affected mainboards to eliminate user confusion.
Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12316
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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On server boards with a recovery jumper, having the fallback path
less sensitive to power fluctuations or BMC issues makes sense.
Increase the maximum number of boot attempts before automatic
fallback to 10 on these boards.
Change-Id: Iabe0b0cbf332686db8e9380a8b65a1477173599c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12320
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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TEST: Booted ASUS KGPE-D16 with single Opteron 6380
* Unbuffered DDR3 DIMMs tested and working
* Suspend to RAM (S3) tested and working
Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I34501d3fc68b71db7781dad11d5b883868932a60
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11965
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I21777283ce0fd3c607951204a63ff67dc656c8cc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11956
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Several ramstage files were inadvertently using Family 10h-specfic
structures, causing unstable operation. Use the K8-specific
structures instead.
Change-Id: I64066dfdca83557393499b77726051e25b814381
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12290
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: I7da84b064287a445fd75a947e2f96ce1ae30d3de
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11954
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The existing KFSN4-DRE support hung during ramstage while initializing
AP #3 if a second CPU package was installed. After analyzing the
Sun Ultra 40 M2 support code it became apparent that the K8 code
cannot function correctly if sequential RAM training is disabled,
and that there were a few other missing calls. This patch adds
the missing calls, adjust the CAR space to an appropriate level, and
explicitly defines the link numbers and connections in devicetree.cb
TEST: Booted ASUS KFSN4-DRE with 2x Opteron 8222 installed.
Change-Id: I96178b7367b0c13de5c9d5d90d032fb0c53639c2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12285
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I0f3297dff47dfb44da034ac6f305dcf1981b9de1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11080
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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These two mainboards contained trivial mistakes related
to FIDVID that broke build when FIDVID was enabled.
Change-Id: Ie7bec77f26ec37eada21308984db4a9fd7a1866f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12226
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is a clone of the original Family 10h-compatible ASUS
KFSN4-DRE board, modified for basic K8 support to allow for
future K8 Socket F Opteron testing.
TEST: Booted KFSN4-DRE with 1 Opteron 8222 processor
KNOWN ISSUES:
* Second CPU package fails to initialize AP
This prevents use of a secondary CPU package
* Second memory channel of at least CPU package #0
does not function (crash at CAR handoff)
Change-Id: I591725babe685fa50a0d7473b17005fbd258056e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12212
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I4f0f6c1cb1fad5b65f196dc6b443252a0ecc70a1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11947
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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