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Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Shuffle words and drop the _DATA_FILE suffix.
Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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These files are directly extracted from the vendor firmware.
Change-Id: I1dea2843255e4a3e93fbb734dea284be029dbc45
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ibe16242d98531ff8e8a696f571496c6f46ea964b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Id572144827b515e9e84c51aa3e4f8a20baf1c212
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Icae1983be6b8c5aebb121be8a383e2613e064122
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26462
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Provide empty stub implementations for set_pcie_reset() and
set_pcie_dereset(), many boards do not provide a proper one.
Change-Id: Ia6811442905ef1776fa5a8e3f5d4433e86e42f88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I5034debc2296352e698898c20910a2d76071e30a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Callsite declared returning int, which makes more sense
than u8 the motherboard side code defined the functions
with.
Change-Id: I8ee83aa2833408ad163c9011a076e08578f3ca6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ifb73f51d34e179ff95b2b1e3ab28adc21717f9ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Along with other patches submitted for review to get the chipset
parts working, this allows Linux or other OS to use a TPM module
plugged into the 20-pin LPC header on the board, by exposing its
presence through the ACPI and PNP tables.
This patch adds to the Kconfig and devicetree.cb files.
Tested with the TPM/FW 3.19 and the trousers tools.
Change-Id: I8c1aea245f81fa44a6bdd5301bbee958cbcdfaaa
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.
Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Since the SIOW method doesn't use any arguments, don't pass it any,
and initialize it as not using any.
Change-Id: I3fa2ab8afb7d09c176a94bbd1db27587c36030cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I71e461b91f981368d4bd13631b868430d1fc5774
Signed-off-by: Noah Glovsky <noah.glovsky@watershedschool.org>
Reviewed-on: https://review.coreboot.org/14530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Incorrect interrupt routing configuration prevented handling
interrupts for devices behind PCIe bridges 00:02.1 and 00:02.5.
With the new configuration, devices work as expected.
Tested with Linux 4.10 booted with the "pci=nomsi" parameter.
Change-Id: I3c95be7ba6207697afc7983d4b5f9d9a28584723
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use of device_t has been abandoned in ramstage.
Change-Id: I8fe817bb514c69a647c2208a0573a2c5fe98722d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I390191fb58605d1bd6a2e5d19a9dfa7c8493e6b2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change OEM ID values to 6 characters to fix error compiling with IASL
version 20180427.
Also update table creator to 8 characters from 7.
Change-Id: Id6c9a7b08dc4a9efeb69011393e29aa5a6bc54c4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I559e71ddc71115167ea4fa380c3c48ac68154f86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25855
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.3 with
kernel 4.9. This code is based on the output of autoport.
Working:
- S3 suspend/resume
- USB
- Gigabit Ethernet
- integrated graphics
- PCIe
- SATA
- eSATA
- PS/2 port (only a mouse has been tested)
- hardware monitor
- onboard audio
- front panel audio
- native raminit (2 x 4GB + 2 x 8GB, DDR3-1333)
- native graphics init with libgfxinit
- EHCI debug. The debug port is the port closest to the HDMI port.
- flashrom, using the internal programmer. Tested with coreboot,
untested with the vendor firmware.
- NVRAM settings. Only `gfx_uma_size` and `debug_level` have been
tested with values different from the default.
Untested:
- VGA BIOS for graphics init
- PCIe graphics
- S/PDIF audio
Not working:
- "clear CMOS" button
The CPUTIN sensor on the Super I/O is not connected. The PECI agent is
likely connected instead to give CPU temperature readings. However,
there does not appear to be enough information in the publicly available
datasheets to fully set up the PECI agent. As a result, there is
currently no accurate, automatic fan control via the Super I/O.
Change-Id: I1fc7940bb139623a5a0fde984c023deca9b551f2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/24971
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add `cmos.default` to get rid of four seconds in romstage. Choose 8 MB
for size for video RAM.
Order the entries like in `cmos.layout`.
Change-Id: If2dcc266f6f061807401b62647124ce96e9a3802
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/23468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Fix the values that were off by one.
This was discovered when using postcar stage that prints with
debuglevel BIOS_NEVER.
Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The variable t32 was originally used to do bitwise operations, but it is
not required anymore. Also, it was assigned twice accidentally, which
introduced a new Coverity Scan defect.
Found-by: Coverity (CID 1385126: (UNUSED_VALUE))
Change-Id: I77afd5064304a36991f63cf1328e13820144efb6
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i82810
Mainboards:
src/mainboard/asus/mew-am
src/mainboard/asus/mew-vm
src/mainboard/ecs/p6iwp-fe
src/mainboard/hp/e_vectra_p2706t
src/mainboard/intel/d810e2cb
src/mainboard/mitac/6513wu
src/mainboard/msi/ms6178
src/mainboard/nec/powermate2000
Change-Id: Ib273316c59f499e6cd3a0e4c4dc4c2cce94ff291
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23300
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Rename tlcl* to tss* as tpm software stack layer.
* Fix inconsistent naming.
Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The PNOT method never notifies the CPU to update it's _CST methods due
to reliance on inexisting variable (PDCx).
Add a method in the speedstep ssdt generator to notify all available
CPU nodes and hook this up in this file.
The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now
relies on code generated in the speedstep ssdt generator. CPUs not
using the speedstep code never included this PNOT method so this is
a logical place for this code to be.
Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i5000
Mainboards:
mainboard/supermicro/x7db8
mainboard/asus/dsbf
Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This source file was mostly copied from ga-945gcm-s2l but had
different IO decode ranges.
Change-Id: I54cb165000fad6984edf13fb33519fb9c9f0350f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Things cleaned up in this patch:
* Add macros for the GENx_DEC registers;
* replace many magic numbers by macros;
* remove many writes to DxxIP since they were 'setting' reset default
values;
* fix some comments about decode ranges.
Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Add code to support the board ASUS AM1I-A. Tested with multiple payloads
and OSes with satisfactory results. S3 suspend/resume works fine with
Linux but has issues with Windows (an exception is thrown). However,
after manually rebooting, Windows resumes the suspended session.
* Tested with: SeaBIOS 1.11 + Linux 4.10 - OK
* Tested with: tianocore vEDK2017 + MS Windows 8.1 - OK
* Tested with: FILO 0.6.0 - hangs after showing the banner
Details are going to be published on the board's status page.
Change-Id: I3d9432849560df81536bbb2ce4c87cd265b820f7
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Removes rs780_before_pci_init() since it was a no-op anyway.
Removes get_nb_rev() since this function is provided via a macro in
the header.
This Makes a lot of function non-static since the header has
prototypes for these.
Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/22603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This logical device is disabled in OEM BIOS. Disable here to match,
since its support is currently incomplete anyway.
Change-Id: I5c07136ec6a14a8ee8cb68537a2663b78fc0fa20
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Updates ACPI tables with work done for asus/p2b-ls, including super I/O
related declarations.
Change-Id: Id2420da4ab04aa5f59ac0aa237d21477a03b826e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add ACPI tables support that will be needed for soft-off and S3 resume in the future.
Boot tested for soft-off.
Change-Id: I28b559406bd53efc555dcbb8282dfe2bd6d1af87
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I6ee86396a1c5aaee248a275b42da801cedace586
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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These typos were found through manual review and grep.
Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I0bf4d6318ade6e931db4f8b1af08db1f9f93c313
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ia21a3e93712bd6b6780fe7308c6cf79c553f4e1b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Add a devicetree option to set temperature adjustment registers
required for thermal diode sensors and PECI. However, this commit does
not have the code needed to make PECI interface actually use these
registers. It only applies to diodes.
As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin
to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3".
PECI, apparently, takes precedence over diode, so the adjustment register
will be set and PECI activated. Or simply use the followup patch, which
makes THERMAL_PECI a mode like THERMAL_DIODE.
I don't have hardware to test THERMAL_DIODE mode, but in case of PECI,
without this patch I had about -60°C on idle. Now, with offset 97,
which was taken from vendor bios, PECI readings became reasonable 35°C.
TEST=Set a temperature offset, then ensure that the value you set is
reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset
Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I907f55622e6aaba401471239f706ab24cd26319f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Note: For some of the boards affected ACPI S3 support
was never tested but feature was just copy-paste from
reference design.
Change-Id: I2a54d605fa267a7501f57efd79a16b3bfa49891e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
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The default for SPI_FLASH_INCLUDE_ALL_DRIVERS is y which already
includes this.
Change-Id: Ib2de0f384a547240528b18f07327566354164699
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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It shares the same northbridge, cpu, romstage with asus/p2b-ls, which is
already on EARLY_CBMEM_INIT as of commit e14d7de.
Change-Id: I8e7c468f0363a5cb9885020bc116e5ae3480ec17
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Boot tested on p2b-ds. Migrate p2b-d as well because they share
the same mainboard romstage.
Change-Id: I3e4b98cc6191d557325fc5da97744902996673af
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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We can simply declare these structures const.
Change-Id: I637c60cc2f83e682bd5e415b674f6e27c705ac91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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