coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-09	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi
2020-04-06	mainboard/cavium: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	mainboard/[a-f]*: Remove copyright notices	Patrick Georgi
2020-03-03	mb/*/Kconfig: Factor out MAINBOARD_VENDOR	Angel Pons
2019-12-19	mb/{cavium,opencellular,roda,scaleway,ti}: Remove unused <stdlib.h>	Elyes HAOUAS
2019-11-28	mb///Kconfig: Drop redundant redeclaration of MAINBOARD_VENDOR	Arthur Heymans
2019-07-29	src/mainboard/{cavium,sifive}: Use $(obj) instead of build	Raul E Rangel
2019-03-20	src: Use 'include <string.h>' when appropriate	Elyes HAOUAS
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2018-11-16	src: Get rid of duplicated includes	Elyes HAOUAS
2018-11-16	mb///Kconfig: Don't specify devicetree path if default val used	Peter Lemenkov
2018-11-16	mb/cavium/cn8100_sff_evb: adjust fmap	Marcello Sylvester Bauer
2018-10-22	mainboard/: Select MISSING_BOARD_RESET appropriately	Nico Huber
2018-10-11	mb/cavium/cn8100_sff_evb: Only expose two UARTs	Patrick Rudolph
2018-10-10	soc/cavium: dynamic UART initialization for cavium cn8100	Jens Drenhaus
2018-08-17	arm64: Factor out common parts of romstage execution flow	Julius Werner
2018-07-30	mb/cavium/cn8100_sff_evb: Compile devicetree for Linux	Patrick Rudolph
2018-07-23	soc/cavium: Enable DRAM test	Patrick Rudolph
2018-07-19	soc/cavium: Add PCI support	Patrick Rudolph
2018-07-17	cavium/bdk: Fix coverity and remove hardcoded DRAM speed	Patrick Rudolph
2018-07-10	soc/cavium: Add secondary CPU support	Patrick Rudolph
2018-07-10	soc/cavium/cn81xx: Set cntfrq_el0	Patrick Rudolph
2018-07-10	mb/cavium/cn8100_sff_evb: Be verbose	Patrick Rudolph
2018-07-10	soc/cavium: Clean uart code	Patrick Rudolph
2018-07-10	soc/cavium: Enable MMU	Patrick Rudolph
2018-07-10	cavium: Add CN81xx SoC and eval board support	David Hendricks