coreboot - Some coreboot project code with my work

Age	Commit message (Collapse)	Author
2008-10-12	Drop tons of duplicated debug.c files, move common file to	Uwe Hermann
	lib/debug.c and use that one. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01	The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of	Carl-Daniel Hailfinger
	code to use it. That makes the code more readable and also less error-prone. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24	Change all occurences of NSC to nsc in the code. The next commit	Uwe Hermann
	will then rename the src/superio/NSC directory to src/superio/nsc. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06	Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-25	arch import user (historical)
	Creator: Hamish Guthrie <hamish@prodigi.ch> Adds a tree for the Eaglelion mainboard. This board has an AMD GX1 processor in a typical Mini-ATX format with a few ISA and PCI slots. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1